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MTI VO filetype

Altera_Forum
Honored Contributor II
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Can somebody explain me what is MTI and the significance of MTI VO filetypes.

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Altera_Forum
Honored Contributor II
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Good question

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Altera_Forum
Honored Contributor II
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MTI = Model Technology Incorporated - this is the original company that developed ModelSim 

VO = Verilog Output file (generated by quartus for simulation of ip cores (http://quartushelp.altera.com/10.0/mergedprojects/eda/simulation/modelsim/eda_pro_msimfull_compile.htm))
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Altera_Forum
Honored Contributor II
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Thanks Schmalisch.. But can you explain me in simple terms the contents of the vo filetype. I think it is only netlists but is there anything else..

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Altera_Forum
Honored Contributor II
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I think this is very clear. The vo file contains Verilog code. 

 

How should I know what exactly it implements? I don't know with which tool or IP core it was generated.
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Altera_Forum
Honored Contributor II
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I am using the crc megacore function. It generates a crc.v and crc.vo . I am just interested to know in general, why do we use vo filetypes, is there any specific advantages while using them in our design.

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Altera_Forum
Honored Contributor II
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Ok, in this particular case the vo file includes a obfuscated simulation model of the CRC core.  

 

For synthesis Quartus will use crc_altcrc.v which is a somehow encrypted implementation.
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Altera_Forum
Honored Contributor II
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Thanks a lot. Is there anyway to view the encrypted file.  

 

I am trying to customize the data generator within the traffic controller module in the following design 

 

http://www.alterawiki.com/wiki/10g_ethernet_and_10g_base_r_phy_interoperability_hardware_demonstration_design  

 

The design provides a script to run the design. But I am writing my own testbench to do the functional simulation in modelsim. But the problem occurs when I try to simulate the data generator module separately (due to the encrypted files). The error says that the modules ( which are in encrypted files) as not found or missing. Is there anyway to overcome this problem.
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Altera_Forum
Honored Contributor II
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For simulating the CRC core just use the crc.vo file. This file includes the functionality of crc.v and crc_altcrc.v. 

 

For synthesis you need the crc.v and crc_altcrc.v file.
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Altera_Forum
Honored Contributor II
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Thanks a lot Schmalisch for the timely advice. . I included all the libraries in my work folder including those of alt_mf. Now I don't have anymore errors during the compilation. I shall now test the design.

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