vdhl code for 7segment display

[Altera_Forum]

i am writing a vhdl code at the moment, am trying to display no 1234 on a 7 segment display but at different times with delay but most time it shows the output at the same time. can anyone help me with that? thanks

[Altera_Forum]

how about posting the code you have already and tell us what the problems are?

[Altera_Forum]

library ieee; 

use ieee.std_logic_1164.all;  Entity seq2 is  Generic ( CLOCK_FREQ : integer := 49999999 ); port (clk : in std_logic;  reset : in std_logic;  PB : in std_logic ;  Tout : inout integer;  x : out bit_vector (6 downto 0) ); end seq2;  architecture Timer of seq2 is  signal clk1 : STD_LOGIC;  signal cntr1s : integer range 0 to CLOCK_FREQ;   begin  process(clk) is begin  if(rising_edge(clk)) then  if(cntr1s=CLOCK_FREQ) then  cntr1s <= 0;  clk1 <= '1';  else  cntr1s <= cntr1s +1;  clk1 <= '0';  end if;  end if;  end process;    process(clk1, reset) is  begin  if(reset='1') then  Tout <= 0;  elsif(rising_edge(clk1)) then  Tout <= Tout +1;  end if;  end process;  end Timer;  architecture structure of seq2 is  constant T1 : integer := 10 ;  constant T2 : integer := T1 + 10;  constant T3 : integer := T2 + 5;  constant T4 : integer := T3 + 20;  constant T5 : integer := T4 + 5;  constant T6 : integer := T5 + 3; begin   process (clk, PB )  begin  if (PB = '0' ) then   x <= "11001111";  elsif   (PB = '1') then  case Tout is  when T1 => x <= "1001111";  when T2 => x <= "0110010";  when T3 => x <= "0000110";  when T4 => x <= "1001100";  when T5 => x <= "0100100";  when T6 => x <= "01100";   when others => Null;  end case;  end if;  end process; end structure;  this is the program i wrote but displays everything at the same time without any delay.

[Altera_Forum]

Two more questions first. 

Why have you got 2 architectures for the seq2 entity? You can only use 1 architecture at a time.  In the testbench you instantiate the seq entity. But the code you posted shows the Seq2 entity. What is the correct code?  Also - please use code tags or post the source files.

[Altera_Forum]

The first architecture is for the timer and the second is for the structure. also i have to enable to just 1 switch to produce the output in sequence.

[Altera_Forum]

library ieee; 

use ieee.std_logic_1164.all;  entity seq2_tb is end seq2_tb;  architecture test of seq2_tb is  signal A: std_logic;  signal s: bit_vector ;  signal B : std_logic;  signal C: std_logic;   begin  instance1: entity work.seq2(Timer)  port map (PB=>A, X=>S ,clk =>B , reset=>C);   S<="1001111" after 10 sec;  S<="0110010" after 15 sec;  S<="0000110" after 20 sec;  S<="1001100" after 25 sec;  S<="0100100" after 30 sec;  S<="01100" after 35 sec; end test;  Another test bench i wrote.

[Altera_Forum]

Because you have only instantiated the timer architecture, there is no switch to select which character.  

 You can only use 1 architecture when you instantiate a component. You need to combine the architectures.