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Does Altera provide the detail delay information for FPGA architecture?

Altera_Forum
Honored Contributor II
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Because I'm not sure whether Altera provides the information or not... 

does anyone know where can I get the information? 

The information is like the register input output capacitance, resistance, delay etc....for the architecture like ALM in Stratix II.  

I'll be very appreciated with your help....
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Altera_Forum
Honored Contributor II
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At least for the delays you should be able to get an idea as soon as you report & display pathes in the (time quest) timing analyzer. Just look at the time increase between an input and output of your desired device. 

 

Coming to resistance and capacitance I don't know, but I had never problems so far with the device, if timing was closed according to the timing analysis, so I did'nt care about...
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