- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
hi,
I want to connect many IO between 2 Cyclone III located on two different cards. I have to make an impedance matching or can I connect them directly ? Best regardsLink Copied
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
This depends on what speed you want to achieve with your interconnection as well as on the wirelength of the logic interconnect.
It is always good to keep the wires of different IO's the same length to get a uniform delay. In case you use unidirectional IO you can connect up IO's from two boards. But notice that you will only be able to communicate at about 50MHz for short interconnect wires. If you do SerDes with accompanying clock for transmission and PPL based synchronization at the receiver side, you can either increase the speed or the wire length. To get higher speeds on a Cyclone III you can use LVDS differential signalling. In this case you need a 100 Ohm resistor at the differential receiving end. Altera devices also have real LVDS inputs that include a 100 Ohm resistor. So you do not need to add it yourself in this case. You should check the device and the specific differential IO pair. In case of LVDS it is also good to keep your wiring symetrical and the same length and layout it on your board with an impedance of of 100 Ohm.- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
For my application i must communicate at 100Mhz (max) with standard I/O. I can't use SERDES or LVDS.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
With short, and equal length, wires and the transfer of the clock, and synchronous signals from one board to the other and recovery of the transmitter clock at the receiving side by means of a PLL 100 MHz is on the edge, but should be possible.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Such a design might have to tackle some significant SSO noise. That’s what differential signaling – with or without an accompanied clock – is all about. It’ll require twice the pin count but can transfer way more than twice the data rate at significantly reduced SSO problems and power needs.
Can you explain what stops you from using LVDS? – Matthias- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page