TimeQuest Constraint examples

[Altera_Forum]

Is there any collection of TimeQuest Constraint examples available somewhere? 

It should be better than the Altera TimeQuest Cookbook, that contains way too few examples.  At the moment I'm looking for examples for AD7626 from Analog Devices that receives a gated input clock and returns a delayed output clock. I guess that the echoed clock is needed to handle the high data transfer rate of 250 MHz. But how should I specify the relations between these clocks and input/output signals? (I can write more details if there is no good examples out there).

[Altera_Forum]

Rysc has written a nice document. 

http://www.alterawiki.com/wiki/timequest_user_guide  Where does the FPGA clock come from? What's it's relation to the clock provided to the ADC? Are you using the echoed clock mode?

[Altera_Forum]

Thanks for the link to Rysc's document, it will probably be helpful. 

 I have an external system clock (sysclk) of 50 MHz that is put into a PLL to create a 250 MHz adcclk. This clock is gated to only generate clock pulses when data is available using ALTDDIO_OUT Module (SCLK). This clock is sent out of the FPGA to AD7626. Since I use echoed clock mode, the AD7626 responds with an equal clock DCO that is delayed min 0, typ 4 and Max 7 ns. DCO is used to collect the Data signal from the AD7626. SCLK or adcclk is used to generate CNV that tells when the AD conversion should start, I guess that CNV should be a little ahead of SCLK to guarantee that SCLK isn't collecting data until the data is ready (after 100 ns).  Currently I have adcclk as a generated clk from the PLL. SCLK is also generated with source from the pll and output after the ALTDDIO_OUT component. DCO is set as a virtual clock in relation to the data pin. But should there be a relation between SCLK and DCO? Is the generated clock from ALTDDIO_OUT valid? SCLK gets a setup time of 2 ns on falling edge from the ALTDDIO_OUT component, which is not what I intended. Should I use multicycle path here? All clocks are somehow related, but with different delays. I also have 2 AD7626 is the system, both with it's own DCO. Should I group the clocks somehow?

[Altera_Forum]

Since you're feeding DCO back to the FPGA and using it to latch_data, you need to have it as a non-virtual clock. 

 Since all those clocks are related, I think it's best to analyze them as such. Here's how I'd go about it -- for 1 ADC.  A bit of Verilog to illustrate  module an_example (sysclk, sclk, dco, d, q); input wire sysclk; output wire sclk; input wire dco; input wire d; output wire q; wire adcclk; pll0(.inclk0(sysclk), .c0(adcclk)); assign sclk = adcclk; reg d_r; always @ (posedge dco)  d_r <= d; reg q_r; always @ (posedge adcclk)  q_r <= d_r; assign q = q_r; endmodule  And the .sdc # Base clock create_clock -name sysclk -period 20 [get_ports sysclk] # PLL clocks  derive_pll_clocks set adcclk {comb_3|altpll_component|auto_generated|pll1|clk[0]} # # Example for 1 AD7626  # SCLK to ADC  create_generated_clock -source $adcclk -name sclk [get_ports sclk] # Tricky part: DCO from the ADC # It is derived from the SCLK but has a 0-7 ns delay # (or a bit more if you account for wire delay)# First, create a derived clock with 0 ns delay create_generated_clock -source sclk -name dco [get_ports dco]# Then use clock uncertainty to represent the 0-7 possible delay set_clock_uncertainty -from dco -to $adcclk -setup 7.0 # Now we can add I/O delays, referenced to the proper clocks  set_output_delay -clock sclk -min ??? [get_ports cnv] set_output_delay -clock sclk -max ??? [get_ports cnv]  set_input_delay -clock dco -min 0.0 [get_ports d]  set_input_delay -clock dco -max 1.0 [get_ports d] # This will calculate the skews and uncertainties for the clocks within the FPGA # the -add is important, otherwise TQ will ignore the uncertainty assignment above and will treat dco as an exact replica of sclk derive_clock_uncertainty -add

[Altera_Forum]

Ah damn, I just noticed something: with a max delay of 7 ns and a clock period of 4 ns, this will not work -- Quartus will never be able to meet the timing constraints. 

All that writing gone to waste...  You need to simply treat DCO as an unrelated base clock, use it to latch the data from the ADC and the use a chain of synchronization registers to pass the data into the adcclk domain.  For constraints, simply use set_false_path or set_clock_groups to cut the paths between DCO and the rest of the clock domains.  create_clock -name dco -period 4 [get_ports dco] set_false_path -from dco -to adcclk