Image processing with VHDL

[Altera_Forum]

Hello, everyone.  

 I am trying to understand a code on image processing. I think i am stuck on the simplest part. :) The bold parts are that i couldn't solve. How can i read a file from outside by VHDL. I prepared a hex file for this code, but i couldn't make the program read it. How can i do that? Would you help me on this part?   When i compile the code, Quartus 9.1 gives error: object "hex_image_file" is used but not declared  Edit: I think i opened thread in wrong forum. Could you move the topic to right forum?  library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_textio.all; use std.textio.all; entity camera is generic( constant filec: in string := "videoinput.hex" ; -- Hex-video file name constant tclk: in time := 100 ns ; -- Clock speed constant ths: in integer := 3 ; -- Horizontal sync time in clock cycles constant tvs: in integer := 29 ; -- Vertical sync time in clock cycles constant tlin: in integer := 8 -- Line time vert. sync generation in clock cycles ); port( signal vdat: out std_logic_vector (7 downto 0); -- Data signal clk: out std_logic ; -- Clock signal n_hs: out std_logic ; -- Horizontal sync signal n_vs: out std_logic ; -- Vertical sync signal dv: out std_logic -- Data valid ); end camera; ------------------------------------------------------------------------------- architecture behav of camera is signal clkx: std_logic := '0'; file image: hex_image_file is in filec; -- File open begin ---- Clock generator ------------------------------------------------------------------------- pclk: process begin wait for tclk; clkx <= not(clkx); clk <= clkx; end process; ---- Camera simulation ----------------------------------------------------------------------- pcamera: process (clkx) variable cnt1: integer := 0 ; -- horizontal sync counter variable cnt2: integer := 0 ; -- vertical sync counter variable cnt3: integer := 0 ; -- horizontal sync counter inside vertical sync begin if clkx = '0' then if cnt1=0 and cnt2=0 then -- Data process time, no vertical or horizontal syncs if not (endfile (image)) then read (image,chr1); -- First character is read if (chr1 = CR) then -- if CR-LF detected, horizontal sync must be generated read (image,chr2); -- Second carachter is read. It must be Line Feed vdat <= (others => '0'); -- Data is cleared cnt1 := ths; -- Horizontal sync time n_hs <= '0'; -- Horizontal sync n_vs <= '1'; -- Vertical sync dv <= '0'; -- Data no valid elsif chr1 = '*' then -- if '*' detected, vertical sync must be generated vdat <= (others => '0'); -- Data is cleared cnt2 := tvs; -- Vertical sync time cnt3 := tlin; -- Line time for vertical sync n_vs <= '0'; -- Vertical sync dv <= '0'; -- Data no valid else -- Hex data chr2hex(chr1,hex_nib); -- First character is converted to std_logic hex2std(hex_nib,idat(7 downto 4)); read (image,chr2); -- Second carachter is read and converted to std_logic chr2hex(chr2,hex_nib); hex2std(hex_nib,idat(3 downto 0)); vdat <= idat; -- Data out n_hs <= '1'; -- No horizontal sync n_vs <= '1'; -- No vertical sync dv <= '1'; -- Data valid end if; else -- If end of file is reached assert (false) report "File end reached..."; -- Console message n_hs <= '1'; -- No horizontal sync n_vs <= '0'; -- Vertical sync dv <= '0'; -- Data no valid end if; end if; if cnt1>0 then -- Horizontal sync generation n_hs <= '0'; n_vs <= '1'; cnt1 := cnt1-1; -- Clock count for horizontal sync time else n_hs <= '1'; end if; if cnt2>0 then -- Vertical sync generation n_vs <= '0'; cnt2 := cnt2-1; -- Clock count for vertical sync time cnt3 := cnt3-1; -- Clock count for horizontal sync time inside vertical sync else n_vs <= '1'; end if; if cnt3=0 and cnt2>0 then -- Horizontal sync generation inside vertical sync n_hs <= '0'; cnt1 := ths-1; cnt3 := tlin+ths; end if; end if; end process; end behav;

[Altera_Forum]

this code is only suitable for simulation, you cannot synthesise it for an FPGA.

[Altera_Forum]

Thank you for reply. 

  --- Quote Start ---  this code is only suitable for simulation, you cannot synthesise it for an FPGA.  --- Quote End ---   Ok, it is not important not to be able to synthesise. I just want to understand the code. Especially to make the code read the hex file part. :)

[Altera_Forum]

What is the point of doing something in VHDL/Verilog that is not synthesizable?  

Sorry i can't help because i've never used VHDL to interpret a file, but the hex part are just bits, you can compare them to other bits that have a meaning and see the info on the file..

[Altera_Forum]

--- Quote Start ---  What is the point of doing something in VHDL/Verilog that is not synthesizable?   --- Quote End ---   I understand you, but as i said, because i want to understand the basics of image processing with VHDL, i am using this code. This is the simplest code i found on internet. :wacko:

[Altera_Forum]

--- Quote Start ---  What is the point of doing something in VHDL/Verilog that is not synthesizable?  Sorry i can't help because i've never used VHDL to interpret a file, but the hex part are just bits, you can compare them to other bits that have a meaning and see the info on the file..  --- Quote End ---    Many reasons - testbenches, Models and things like that. There is a large part of VHDL that is unsynthesisable (file IO, pointers, protected types etc).  Mucahid - You need to run this code in modelsim - not quartus. the simulator in quartus (and is only available in older versions of quartus, it was dropped in V10) is very basic and requires that you synthesise the code befoer you can simulate. Because the code is unsynthesisable there is the problem. You need to run it in modelsim.  Secondly - there is no type "hex_image_file" declared - hence the error. You need to delcare the type yourself.   thirdly - this file is using very old syntax (VHDL 1987). I suggest using VHDL 93. VHDL is very good at reading text files but not good at reading anything else.   I suggest reading a textio tutorial online

[Altera_Forum]

--- Quote Start ---   Mucahid - You need to run this code in modelsim - not quartus. the simulator in quartus (and is only available in older versions of quartus, it was dropped in V10) is very basic and requires that you synthesise the code befoer you can simulate. Because the code is unsynthesisable there is the problem. You need to run it in modelsim.  Secondly - there is no type "hex_image_file" declared - hence the error. You need to delcare the type yourself.   thirdly - this file is using very old syntax (VHDL 1987). I suggest using VHDL 93. VHDL is very good at reading text files but not good at reading anything else.   I suggest reading a textio tutorial online  --- Quote End ---    Thanks for your advices. I will do as you said, i hope i manage it. :)