DAC (DAC5672) and ADC (AD9254) in VHDL

[Altera_Forum]

Hi, 

i have a project in which i need to create the VHDL code for a DAC (DAC5672) and an ADC (AD9254). It is part of a CDMA.  The DAC must incorporate a 2's complement and the ADC must incorporate an offset binary.  This is what i have so far :  this is my adc which i am pretty sure will work ok :  entity adc is port(  clk : in std_logic;  adc_out : out std_logic_vector(13 downto 0);  analog_in : in std_logic_vector(13 downto 0)  ); end adc;  architecture behavioral of adc is signal msb : std_logic; begin  process(clk)  begin  if(clk'event and clk ='1') then  adc_out(12 downto 0) <= analog_in(12 downto 0);  msb <= analog_in(13);  adc_out(13) <= not msb;  end if;  end process; end behavioral;    this is my dac which i am pretty sure is no good :  entity dac is port(  clk : in std_logic;  digi_in : in std_logic_vector(13 downto 0);  analog_out : out std_logic_vector(13 downto 0)  ); end dac;   architecture behavioral of dac is signal analog_signal : std_logic_vector(13 downto 0); begin  process(clk)  begin  if(clk'event and clk ='1') then  analog_signal <= digi_in;  analog_signal <= not(analog_signal) + "00000000000001"; -- complément à 2  end if;  end process;  analog_out <= analog_signal; end behavioral;   Please could someone point me in the right direction for either of the codes if they think something could be made better ?  Thanks.

[Altera_Forum]

Well, the code for the ADC controller is wrong. The msb of adc_out is delayed by and extra clock cycle compared to the rest of the word.  

And in your ADC code, your analog_out is just a counter (that will actually not work in simulation). This is because you have assigned analog_signal to digi_in, but then overridden this assignment.. In VHDL, signals get assigned the last thing assigned to them. They are not like variables that are updated immedietly

[Altera_Forum]

ok, so for the ADC, would this work ? 

  if(clk'event and clk ='1') then  adc_out(12 downto 0) <= analog_in(12 downto 0);  adc_out(13) <= not analog_in(13);  end if;  Now the MSB and the rest of the word are synchronised right ?  And for the DAC, would it be better to replace analog_signal directly with analog_out ? Although i don't see how this will convert a digital signal to an analogue signal...

[Altera_Forum]

--- Quote Start ---  ok, so for the ADC, would this work ?   if(clk'event and clk ='1') then  adc_out(12 downto 0) <= analog_in(12 downto 0);  adc_out(13) <= not analog_in(13);  end if;  Now the MSB and the rest of the word are synchronised right ?   --- Quote End ---    Yes, now synchronised     --- Quote Start ---   And for the DAC, would it be better to replace analog_signal directly with analog_out ?   --- Quote End ---    Note quite. You'll still have the same problem. Ill let you think about it....    --- Quote Start ---  Although i don't see how this will convert a digital signal to an analogue signal...  --- Quote End ---    It wont, unless this is the number format that your external DAC chip requires.

[Altera_Forum]

Would this do ? 

  process(clk)  begin  if(clk'event and clk ='1') then  analog_out <= not(digi_in) + "00000000000001"; -- complément à 2  end if;  end process;  I don't think this is right because i'm not sure i can directly send the in to the out of the DAC, i think i have to go through a signal (which is why i did the code like that in the first place) but like this analog_out is only assigned once and is not overwritten i think ?

[Altera_Forum]

This is correct in that analog out has been inverted properly. 

But you are getting confused. An FPGA cannot have any analogue inputs or outputs. The input/output is digital. The external DAC and ADC will do the conversion.

[Altera_Forum]

Ok, thanks you for your help. 

Yes, now that you say, i understand. I will now create some test benches and see what it gives me.