Can the setup/hold time violated be removed with TimeQuest?

[Altera_Forum]

I am a beginner in STA using TimeQuest. Now I have a basic understanding about STA using TimeQuest. I have a question which confused me: 

 Take an example, if in a design, there is a path, from node "a" to node "b". Both launch and latch clocks are "clk", whose the period is 10ns. And the default setup and hold relations (10ns, 0ns) are right.   However, in this path, the setup (or hold) time is violated, my question is whether this violated can be removed through TimeQuest like put constrains in .sdc file or any other approach?   In my understand, it can't be removed. In this case, it means my design failed to meet time requirement and I need to modify my design, right?  Hope anyone can help me, thanks very much.

[Altera_Forum]

Well through .sdc file you can guide the timequest to do correct constraining. 

Constraints like target clock frequency,false paths,multicycle paths etc if there are to be set.   Now supposetake an example there is a path between asynchronous clock domain then its is bound to fail timing and in that case a false path needs to be set.   Now coming to what you mentioned that point a and b are in the same clock domain with time period 10ns then provided other constraints are proper (you have taken care of false paths or multicycle paths if any) in the design then i think you need to review your RTL. If you are failing by some 10 Mhz then you can try some optimization switches through .qsf file. I have seen these optimization switches improving the design performance by 20 MHz also.

[Altera_Forum]

--- Quote Start ---  Well through .sdc file you can guide the timequest to do correct constraining. Constraints like target clock frequency,false paths,multicycle paths etc if there are to be set.   Now supposetake an example there is a path between asynchronous clock domain then its is bound to fail timing and in that case a false path needs to be set.   Now coming to what you mentioned that point a and b are in the same clock domain with time period 10ns then provided other constraints are proper (you have taken care of false paths or multicycle paths if any) in the design then i think you need to review your RTL. If you are failing by some 10 Mhz then you can try some optimization switches through .qsf file. I have seen these optimization switches improving the design performance by 20 MHz also.  --- Quote End ---    Thanks very much, so generally speaking, my understanding is right. I don't know what is .qsf file and I have never used it. I should investigate what it is and how to use it.   The most common approach in my case seems to be: the path from "a" to "b" failed, then we can try to break this path through add a register between then to add a pipeline.

[Altera_Forum]

The .qsf is the Quartus setting file. 

When needed, you may be able to improve timing by fiddling with the Quartus synthesis/fitting options. Also, sometimes manually placing some cells can also improve timing a bit.

[Altera_Forum]

--- Quote Start ---  The .qsf is the Quartus setting file. When needed, you may be able to improve timing by fiddling with the Quartus synthesis/fitting options. Also, sometimes manually placing some cells can also improve timing a bit.  --- Quote End ---    Thanks. Yes, fiddling with the Quartus synthesis/fitting options may work in some cases, but the options are very limited.  You mentioned "manually placing some cells", do you mean put a register in a failed path to increase a step pipeline as I described?  Thanks.

[Altera_Forum]

--- Quote Start ---  Thanks. Yes, fiddling with the Quartus synthesis/fitting options may work in some cases, but the options are very limited.  You mentioned "manually placing some cells", do you mean put a register in a failed path to increase a step pipeline as I described?  Thanks.  --- Quote End ---    Unfortunately the person answering this is completely wrong.  Timequest set_output_delay and set_input_delay constraints are used to set the external PCB and device input and output delay (including setup and hold time). Timequest does a very good job of this. There is no need to be fiddling with manually placing cells. Search for TimeQuest User Guide by Ryan Scoville.