I'm currently writing an image processing module on a Cyclone IV E. The module has two input ports iEN (enable) and iVAL (value). Output ports are labeled oEN and oVAL. For simple image processing filters using bitshifts the timing constraints are easily met. For filters that require a division operation, however, timing constraints were violated. So I added a multicycle between the divider's operand register outputs and the oVAL and oEN register inputs.
Gate level simulation shows correct behavior but I would like to know if it's possible to simulate the multicycles at RTL level. It appears that the multicycle constraints in the sdc file are ignored for RTL simulation.
Simulating at RTL level would allow me to simulate various image sizes more efficiently instead of having to generate a new netlist for each test size.
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