Dear forum members :
A general question on reset.
1) Does the internal POR in Cyclone II device initialize all the config SRAMS to 0? - meaning will the "state machine state bits" be reset to 0's ?
2) After configuration, should there be a User Reset signal (hard reset) to initialize the chip , and bring it to a known state , includign IOs?
3) Can the user "reset" be hard reset or a soft reset ? If yes, should they be synchronous resets?. If the hard reset is not synchronized to a user clock ,where as "soft reset" is a "Q" of a register (flip-flop) bit , will the device function properly? - In this case the "soft reset" doesn't seem effective.
4) Is there a synthesys directive to specifiy an initial condition for flops ( state machine states) , in case "hard reset " is not available and the "soft reset" doesn't function?
thanks for the help
...lifesec
