Cycle-Accurate Power Estimation for Altera Devices

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Cycle-Accurate Power Estimation for Altera Devices

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Hello,

I'll be doing some analysis which requires at least cycle-accurate power estimations. From what I gather, the PowerPlay tool only calculates total power consumption.

I've also looked into Synplify, but from what I can tell the only benefit of this is that you are given finer-grain control over the synthesis process. Is it possible to use other Synopsys tools such as PrimePower or Primetime-PX to calculate cycle-accurate power on the Synplify synthesized designs? I don't think so, since there is no .cdl for the Altera device available - at least not that I know of.

Any suggestions on what tools/methodology can be used to estimate cycle-accurate power from the placed-and-routed netlist would be much appreciated! I'm using a CycloneIII FPGA.

-k

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