Hi - I'm a newbie to the forum and have a question regarding PLL and dedicated output on a Cyclone III device.
I have a design which involves SDRAM, and so far I've been developing it using a DE1 Cyclone 2 board, which has a single 16-bit-wide SDRAM chip.
Now I'm using a Cyclone III board which has a pair of 8-bit wide SDRAMs, which I want to gang together and treat as though it were single 16-bit chip. I have a single PLL generating three identical 100MHz outputs - one running each chip, and one running the rest of the design (separated so that I can introduce phase shifts should it become necessary.)
The problem is this: each SDRAM has its clk pin connected to a dedicated PLL output on the FPGA, but of course a single ALTPLL instance can't drive both dedicated outputs, so I'm getting a compile warning about one of the clocks using non-dedicated routing.
So far this isn't causing a problem, but I'd like to solve it the "right" way if I can. So my question is this:
Is it possible, and if so, what's the best way to drive the second dedicated PLL output? Can I just instantiate a second ALTPLL instance specifically for the second clock, and drive it from the same 50MHz input clock as the first one? Or can I chain the PLLs somehow? Or do I just have to live with the non-dedicated routing and hope it doesn't cause a problem as the design expands?
