PLL: Clock switchover (Cyclone III)

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

PLL: Clock switchover (Cyclone III)

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I have a doubt with the automatic clock switchover. I'm trying to connect two clocks of 168 Mhz as inputs of a pll, when one of this is available, the other is not and vice versa. Does anyone know if it is necessary that the second is running before the current reference clock is not present?

Thanks in advance.

Cris

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