- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi
I would like to connect several inputs PLL on the same input port signal. Is it possible? The frequency input of the ALTPLL is 66MHz. I obtain a warning Warning: The parameters of the PLL Clk65MHz: pll1 do not have the same values - hence these PLLs cannot be merged Info: The values of the parameter "Min Lock Period" do not match for the PLL atoms --- Quote End ---Link Copied
2 Replies
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
PLLs need to be driven by dedicated clock inputs. The connection capcbilities are different for FPGA families, refer to the clock network chapter in device handbook, or ask specifically.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello FvM
thank a lot for your reply.
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page