Signals removed during synthesis - lost fanout

[Altera_Forum]

Hi, 

 I am hoping someone can help me with this, I have a design written in VHDL which I have operational under RTL simulation. When I try to complie the design for Gate-level simulation a number of registers are removed due to "lost fanout". Having looked into the problem I'm not sure how to solve it in my case. I believe the problem occurs when the signals in question aren't connected to an output? I have a top level design in which I declare a number of components, many of which I have also designed, that I then trigger/enable from the top level design to perform different functions. When people say "register is not connected to an output" is that referring to the outputs of the top level design only, e.g do the lower level component signals need to feed back to the outputs of the top level design or can the top level design enable/trigger an event in a lower level component and then not bother about it? Some of the registers removed in my opinion aren't supposed to be outputs either for example enable signals to the lower level components and inputs to floating point ALU's (Altera IP floating point ALU's). In the case to the ALU's I'm using them to process some incoming data before storing the result in DPRAM (in the top-level design) so of course this is not feeding an output but it is very useful!   David

[Altera_Forum]

Would I be right in thinking I need to make use of the noprune VHDL synthesis attribute to solve this problem?  

 Thanks

[Altera_Forum]

All signals that have no direct or indirect effect on the design output will be removed. The "useful" signals you refer to would be expected to have an indirect effect on the design output, I assume.  

 You should consider however the case, that some signals that are thought to be essential for the design are actually ignored due to design errors.  Noprune can also keep registers that are meaningless for the design output.

[Altera_Forum]

Thanks for the reply, 

 No Prune seems to have solved my problem for the moment :). I was setting up an LUT which now seems to be OK under both RTL and Gate level simulation. Gate level simulation takes an eternity though!   RE: design errors are you referring to the way in which the design is implemented? Wouldn't I get an error message or at least a warning or info message if that were the case?   David

[Altera_Forum]

If you leave logic in that ultimately does nothing, why do you want to leave it in? IMHO, the only reason to include noprune is for signals you want to debug with signaltap that is only there for monitoring in signal tap. Otherwise its just wasted logic that does nothing.

[Altera_Forum]

Its not that the signals ultimately do nothing, just that they never directly effect the output. The part I was having trouble with was being used to populate a look-up table - without this nothing else would work correctly thereafter but all that the logic was doing was manipulating some data and storing it in memory - not effecting an output. Its working fine now :cool::)

[Altera_Forum]

but I still dont get it - surely a look up table is just a ROM (unless the LUT comes from an external source)? you shouldnt need logic to generate a ROM table, it should just be constant,

[Altera_Forum]

I decided to do it this way because my LUT needs to be reconfigurable, I'm using it to convert 14 bit current samples into 32 bit, the 32 bit result depends on the current range which I want to be able to change if desired. Otherwise you are quite right I would have used a ROM LUT.

[Altera_Forum]

but the fact that you can change it from an external source should mean it doesnt get removed. So I still suggest that part of the design is wrong.

[Altera_Forum]

--- Quote Start ---  Its not that the signals ultimately do nothing, just that they never directly effect the output. The part I was having trouble with was being used to populate a look-up table - without this nothing else would work correctly thereafter but all that the logic was doing was manipulating some data and storing it in memory - not effecting an output.  --- Quote End ---  I agree with Tricky, if you really need a no prune here it means there is something wrong with your design. A register/signal is only optimized away if it never has any chance of affecting any output, ever. If there is any way the contents of that memory affects one output, even a lot of cycles after it was written to, then it won't be optimized away by the synthesizer.