Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20704 Discussions

Arria II EP2AGX45CU17C6N power up failure.

Altera_Forum
Honored Contributor II
1,583 Views

Hi all, 

 

I am using Arria II EP2AGX45CU17C6N FPGA in my PCIe interfacing card project, I had only one FPGA device mounted on PCB and power section. 

 

Power voltage rail on PCB board 

 

3.3V & 0.9 (sw_reg - Dual O\P) 

2.5V (LDO) 

| | 

1.5 & 1.1V (LDO - Dual O\P) 

 

On doing Initial power supply check in PCB only some FPGA VCC pins 

 

Receives voltage Vccio = 3.3V , Vcc =0.9V ,Vccl_GXB=1.1V,VccH_GXB=1.5V  

 

And VCCA=2.5V. 

 

but other pins like vcca_pll(2.5v),vcc_pll(0.9v) and vccb(1.5v) are open 

 

(isolated from getting powered by removing ferrite bead component on pcb) 

 

At this point I measured Voltage rail, all voltage output are fine and as per expected (no Heat on FPGA and regulators) 

 

 

 

After some time i mounted all the components and powered up the board  

 

so that other VCC and PPL pins also receives voltage VCCA_PLL 

 

(2.5V),VCC_PLL(0.9V) and VCCB(1.5V),At this time I found VCCB(1.5V)  

 

Pins got shot to GND pin also 1.5V LDO and FPGA got heat. I switched of  

 

Supply and check the impedance now VCCB pin of FPGA and GND Pin is  

 

Short (Z = 0 ohm),  

 

I came to know VCCB pin of FPGA got gone bad,  

 

my query, 

 

1. Can i connect only some FPGA VCC pin to respective voltage initially (not connecting PLL and VCCB pins,. connecting these PINs second time power on)?? Will devices pin go bad on second power up??  

 

2. Should I connect all the power supply pin of FPGA including PLL and VCCB every time power up for device to work properly?? not to get spoil of any pins?? 

 

 

Note:- 

Last option... I might have received fault\damage FPGA but it’s my last option getting bad FPGA chip from standard manufacturing is very least possibilities...
0 Kudos
21 Replies
Altera_Forum
Honored Contributor II
750 Views

I have the same problem. Did someone found anything?

0 Kudos
Altera_Forum
Honored Contributor II
750 Views

The device with not work properly if it doesn't get poser an all its supply pins. The POR circuitry will prevent the FPGA from starting. AFAIK it shouldn't do any permanent damage, but still I wouldn't recommend to do it. 

Are you sure of your PCB? You could have connected some VCCB or VCC_PLL pins to ground by mistake.
0 Kudos
Altera_Forum
Honored Contributor II
750 Views

Hi thanks, 

I am sure and checked the VCCB and VCC_PLL pins are not shorted to gnd on my PCB.. also i check impedance of board after full PCB assyembly (Zo) it shows some value NOT SHORT to GND... 

 

Only on second time power up of board (fist time power to VCCB and VCC_PLL) these pins got short to GND (Zo=0)... 

 

I am analyzing the causal..?????  

 

since FPGA IC is costly getting one more IC's takes long time and process.  

 

And  

 

i afraid same issue could reflect on new one too...?????????
0 Kudos
Altera_Forum
Honored Contributor II
750 Views

Are you sure your power supplies are working correctly? Do they produce the right voltage, and is there any overshoot at power up that could damage the FPGA?

0 Kudos
Altera_Forum
Honored Contributor II
750 Views

Yes my power supply rail voltages are correct and most supplies derived from LDO except 3.3V and 0.9V... 

 

Does Arria II EP2AGX45CU17C6N have any specific power sequencing…??  

 

Can I power up VCC, VCCIO, VCCL_GXD, VCCH_GXB, VCCA first and after some time (adding ferrite filter component and) powering up VCCB, VCCA_PLL and VCCD_PLL voltage pins, along with initial supplies…?? 

 

I faced problem at second time power up ie. VCCB and VCC_PLL along with initial supplies…
0 Kudos
Altera_Forum
Honored Contributor II
750 Views

No, as far as I know the modern Altera FPGAs are pretty forgiving with power sequencing. And even there, at worst it would lead to some startup problems, it shouldn't cause a short on some VCC pins. I'm sorry but if there indeed isn't any overshoot of some power lines at startup I don't see what could cause this. 

Are you sure the short is in the FPGA itself and not the LDO or a filter between them?
0 Kudos
Altera_Forum
Honored Contributor II
750 Views

Yes, I am sure the short is in FPGA vcc pins itself, neither in LDO , filter circuits etc., 

 

In fact I removed LDO,Filter(and associated passive connecting b\w FPGA and GND) still short persist. 

 

so, we removed FPGA from PCB and check the VCCB,VCCL_GXB and VCCH_GXB pin balls it Shown short to GND in multimeter.
0 Kudos
Altera_Forum
Honored Contributor II
750 Views

The only reasons I know of that could explain these kind of failures are ESD and an overshoot on the power supplies. Some DC/DC converters that are a bit overcompensated can overshoot at startup and supply a voltage that is over the expected value for a short time, and this can destroy the FPGA.

0 Kudos
Altera_Forum
Honored Contributor II
750 Views

Hello everybody, 

I have a question, we have a similar problem on a few pieces of Arria II GX EP2AGX65DF25C6. After power up we found VCCA_PLL(2.5V) pins shorted to GND. Power supply rail voltages are correct and without overshooting. Power supplie 2.5V are derived from LDO and filtered. 

Thank you very much for your answer.
0 Kudos
Altera_Forum
Honored Contributor II
750 Views

 

--- Quote Start ---  

Hello everybody, 

I have a question, we have a similar problem on a few pieces of Arria II GX EP2AGX65DF25C6. After power up we found VCCA_PLL(2.5V) pins shorted to GND. Power supply rail voltages are correct and without overshooting. Power supplie 2.5V are derived from LDO and filtered. 

Thank you very much for your answer. 

--- Quote End ---  

 

 

Hi, 

Is VCCA_PLL(2.5V) pins all De-Caps mounted before power up..??
0 Kudos
Altera_Forum
Honored Contributor II
750 Views

Hello, 

yes, all De-Caps for VCCA_PLL(2.5V) are mounted before power up.
0 Kudos
Altera_Forum
Honored Contributor II
750 Views

hi 

 

have you found the cause of FPGA's PLL power pin shorted-circuit to GND. 

we have same problem in 2 of our boards. we are using EP2AGX95EF35C4N. 

VCCA_PLL pins are shorted to GND. 

 

Regards, 

Arvind.
0 Kudos
Altera_Forum
Honored Contributor II
750 Views

Hi, 

Yes as per RMA result FPGA IC is prone to overshoot of supplies. 

And as per my analysis, There could be two reasons one Overshoot \ Voltages on rail out of tolerance (Eg:- 1.5V vccb could be 1.425 - 1.575) and other cause may be ESD.......
0 Kudos
Altera_Forum
Honored Contributor II
750 Views

hi, 

we are using linear power supply, and its with in the range.there is no overshoot. 

chances of ESD is less in our case. 

what type of filtering you are using for pll supply? 

 

regards, 

Arvind.
0 Kudos
Altera_Forum
Honored Contributor II
750 Views

the board was working for 1 year, before it failed with VCCA_PLL shorted to GND.

0 Kudos
Altera_Forum
Honored Contributor II
750 Views

Hi we use, 

Ferrite bead Chip 33 ohm @ 100Mhz as PLL supply filter. 

can you see your FPGA board power rail voltages and IC used...??
0 Kudos
Altera_Forum
Honored Contributor II
750 Views

Hello arvindk, we had a similar problem with ARRIA II GX EP2AGX65DF25C6 (after power up we found VCCA_PLL(2.5V) pins shorted to GND). We had two pieces of FPGA in Altera Failure Analysis Center in Malaysia and they said us, that we damage the die of lidless FCBGA package(bottom corner) by mounting a heat-sink with push pins. Do you use a heat-sink?

0 Kudos
Altera_Forum
Honored Contributor II
750 Views

Hi Joey, yes we are using heat-sink with push pins from AAVID (10-5607-05G). we are also using lidless FCBGA package, and its bottom right is damaged. So this could be the reason. we will be sending the FPGA to Altera Failure Analysis Center soon. We replaced the FPGA and now its working. our board was proto board and we had removed the heatsink couple of times.

0 Kudos
Altera_Forum
Honored Contributor II
750 Views

heat-sink with push pins from AAVID (10-5607-05G). www.aavid.com/products/bga/10-5607-05g .

0 Kudos
Altera_Forum
Honored Contributor II
672 Views

Hi arvindk, we solved the problem by using a gap-filler between heat-sink and chip. If you would like more information(our solution, application notes...) I can give you via email. If you can, write me a email address.

0 Kudos
Reply