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Hi. I am learning systemverilog. I have a simple design accumulator(DUT). Stimulus is randomized every cycle in a task and accumulated result is monitored. Result is:# * ERROR * DUT acc is 0 :: SB acc is 2# * ERROR * DUT acc is 0 :: SB acc is 2# * ERROR * DUT acc is 2 :: SB acc is 3# * ERROR * DUT acc is 2 :: SB acc is 5# * ERROR * DUT acc is 3 :: SB acc is 11
SB(scoreboard) is always 2 cycler earlier. I have try a lot of ways to delay the scoreboard but all in vain. How to delay data generated by randomize for 2 cycle? source code is attached. i really appreciate that you take ur time to look at the code and reply. Thanks a lotLink Copied
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