questions of byte enable for PCIeIP_AvalonMM.

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

questions of byte enable for PCIeIP_AvalonMM.

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Hello,I am a green hand of FPGA field.And right now I am designing a FPGA PCIe--IoBUs bridge using EP4CGX15.

In the IP doc,It is said:"To improve PCI Express throughput, Altera recommends using an Avalon-MM burst master without any byte-enable restrictions."

What does it mean?

To disable the byte enable?Or I should use a Avalon-MM master which the MASTER doesn't have byte-enable restirctions?

Best Regards~

Young SuitJune

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