Downloading data directly to FPGA (not FPGA configuration)

[Altera_Forum]

I'm doing some heavy algorithm stuff in a Stratix IV eval kit. I need to download large amounts of test data to external memory (SDRAM, SRAM, etc.) from windows, process the data in the FPGA, retrieve the results and dump it to a text file that I can read with MATLAB. Is anyone familiar with an convenient ways of getting data into/out of FPGAs? There is Ethernet, JTAG (both usb and header based), PCIe edge connector, HSMC connector on board. I don't have any software programming support, so it would have to be something a firmware guy could easily figure out.

[Altera_Forum]

For any of those connections, you would need some software support to read/write data from a PC. 

Mathworks allows connection directly to/from a board from simulink via Ethernet, but the last I checked they only supported Xilinx boards, with Altera Dev boards to be supported in future. You also need HDL coder for this connection AFAIK.

[Altera_Forum]

--- Quote Start ---  I'm doing some heavy algorithm stuff in a Stratix IV eval kit. I need to download large amounts of test data to external memory (SDRAM, SRAM, etc.) from windows, process the data in the FPGA, retrieve the results and dump it to a text file that I can read with MATLAB. Is anyone familiar with an convenient ways of getting data into/out of FPGAs? There is Ethernet, JTAG (both usb and header based), PCIe edge connector, HSMC connector on board. I don't have any software programming support, so it would have to be something a firmware guy could easily figure out.  --- Quote End ---    Assuming you are referring to either the "Altera Stratix IV GX Development Kit" or the "Terasic DE4", both boards are PCIe boards, with ethernet, JTAG, HSMC, etc.  You can use JTAG as described in: http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial  You can use PCIe as described in: http://www.alteraforum.com/forum/showthread.php?t=35678  The zip file includes a program called pci_debug, which allows you to access the PCI board from Linux. This uses CPU reads and writes, so the performance is not that great. For high-performance, you need to use a DMA controller on the Stratix board, and then write a device driver to utilize it.  You could consider using the Ethernet interface. The code from your development PC is pretty simple - the JTAG tutorial has a client and server written in Tcl, and a client written in C-code. You'd just have to instantiate a NIOS II processor on the Stratix IV board, and write NIOS II code for transferring data to/from memory.  Cheers, Dave

[Altera_Forum]

I did a similar thing with a Cyclone IV evaluation kit.  

I created a stand-alone project that had a RAM with the test data (from a .mif file) and wrote that data to the SDRAM. After that I wrote a wrapper for my algorithm that read the data from the SDRAM (simulating real-time data input in my case), the algorithm processed the data and then I used SignalTap to read the data from the algorithm output. I used the "export file" option in SignalTap, exported the data to CSV and then checked it in Matlab. Note that you need to keep the evaluation board powered after writing the SDRAM so that it will not be erased. Hope this helps.

[Altera_Forum]

--- Quote Start ---  I'm doing some heavy algorithm stuff in a Stratix IV eval kit. I need to download large amounts of test data to external memory (SDRAM, SRAM, etc.) from windows, process the data in the FPGA, retrieve the results and dump it to a text file that I can read with MATLAB. Is anyone familiar with an convenient ways of getting data into/out of FPGAs? There is Ethernet, JTAG (both usb and header based), PCIe edge connector, HSMC connector on board. I don't have any software programming support, so it would have to be something a firmware guy could easily figure out.  --- Quote End ---    You can download a free demo of the WebPHY DATABUS IP Core from here: http://www.webphyfpga.com  The IP core can send and receive data between a FPGA and MATLAB over Ethernet using its web-based "rd" and "wr" commands, wrapped in MATLAB's "urlread" command. The core also has a user-customizable web page allowing browser-based control of the FPGA. The core connects to Ethernet via standard LVDS-configured IOBs on the FPGA. No external PHY or DDR/Flash memory chips, software TCP stack or embedded CPU are required - everything is contained within the core.