qsys port export and internal wiring

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qsys port export and internal wiring

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Hello!

I´ve got a question regarding qsys system. Is it possible to use a port of an IP block for internal wiring to another IP block and for export to my top sheet (as it was in SOPC).

e.g.: i´ve IP_compiler for PCI Express. In my QSYS System i use pcie_core_clk as a clock source for DMA, Onchip,... How can i export this clock signal? Is it somehow possible to make this happen "automatically" or do i have to use a PLL or a different IP block for exporting this signal ?

thanks for ur help

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