What are "worst case path" and "critical path", how are they similar or different?

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

What are "worst case path" and "critical path", how are they similar or different?

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Critical path is the path that takes the longest duration to complete in the circuit, it is between 2 registers. Making the clock cycle any smaller may result in this being failed and thus it is called critical path, right?

Than what is worst case path and how are these 2 related?

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