Active-HDL Disable SystemVerilog

Intel® Quartus® Prime Software

Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

Active-HDL Disable SystemVerilog

1,457 Views

Hello,

Is it possible to disable SystemVerilog assertion module within Active-HDL? The feature is not currently purchased by my company and I keep getting the following error.

# ELBREAD: Error: You do not have a valid license to simulate SystemVerilog assertion module 'rldram_example.genblk220'.# Contact Aldec for ordering information - sales@aldec.com.# ELBREAD: Error: Elaboration process completed with errors.

Link Copied

0 Replies

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.