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Additional circuit within a circuit - if then else

Altera_Forum
Honored Contributor II
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Hello, 

 

I am a beginner to VHDL and currently have an assignment to complete. It is as follows: 

 

 

  • A digital circuit has two 4-bit inputs a
 

 

I have written the architecture correct for the subtractor part. This fully compiles. When I try to write the subcircuit for the If Then Else part about the 'the circuit has a single bit output t that is to be high if the result of the subtraction is zero' part I struggle.  

 

This is my code so far 

 

entity ComparatorSubtractor4Bit is port ( 

a,b : in integer range 0 to 15; 

borrowin : in integer range 0 to 1; 

sub : out integer range 0 to 15; 

t : out integer range 0 to 1); 

end ComparatorSubtractor4Bit; 

 

architecture Adder of ComparatorSubtractor4Bit is 

begin 

sub<= a - b - borrowin; -- note borrow out will be sub[4] 

process (a,b) 

begin  

if sub<= 0 then t<=1; 

else t<=0; 

end if; 

end process; 

end Adder; 

 

I have written a sub If Then Else code on a previous assignment which involved the inputs being compared, however it seems to have a problem when I try to If Then Else the output.  

 

Any help would be greatly appreciated 

 

Sam
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Altera_Forum
Honored Contributor II
373 Views

Thje error message seems self-explanatory to me, isn't it? 

 

--- Quote Start ---  

Error (10309): VHDL Interface Declaration error in test.vhd(17): interface object "sub" of mode out cannot be read. Change object mode to buffer. 

--- Quote End ---  

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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

Thje error message seems self-explanatory to me, isn't it? 

--- Quote End ---  

 

 

No, I don't really know what the error messages mean. Like I say I'm just a beginner. Could you explain further?
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Altera_Forum
Honored Contributor II
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You cannot read (eg. check the value of) an output port. Either create a temporary internal signal or change the mode from "out" to "buffer". 

 

sub : buffer integer range 0 to 15;
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