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Sine wave simulation

Altera_Forum
Honored Contributor II
‎01-08-2013 11:22 AM
1,218 Views

I have a code for generating sine wave in VHDL. But i dont know how to simulate it. Any DAC simulator available ....????pls help me...its urgent

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Altera_Forum
Honored Contributor II
‎01-08-2013 11:59 AM
498 Views

In what form is the output? std_logic_vector? 

 

In modelsim you can change the representation of the signal into "analog". The simulator then draws the sine wave if the design is correct.
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Altera_Forum
Honored Contributor II
‎01-08-2013 01:24 PM
498 Views

Is there any option in Qsim.....????

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