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Hello,
I'm just going to insert into my QSys system, an SPI slave Avalon MM bridge. MISO / MOSI / SCK / nSS are physically connected to an AVR XMega. The XMega acts as SPI master. The QSys contains an Avalon MM Master (VHDL interface to other logic), a PLL and a clock source. In QSys system is a SDRAM controller included (to access a 32MB SDRAM on my DE0-Nano board). The address range is 0x0000_0000 - 0x01ff_ffff (read_master and write_master). The SDRAM-access works well with my VHDL-Avalon MM Master. I am on the search for a relevant documentation, and examples, that describe howto the access the memory area of the SDRAM controller via SPI. www . altera . com / literature / hb / nios2 / external_processor_if.pdf (page 11-12) explains that this is possible. It is not my problem to send or receive data via SPI (in my XMega firmware). My questions are how do I set one avalon addresses via SPI? How data can be read via SPI? How are the data packets look like? Is there a protocol for this purpose? Maybe i missed something. Kind regards KaiLink Copied
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The SPI-to-Avalon-MM interface is not very well documented. Its very similar to the JTAG-to-Avalon-MM interface - JTAG serial transactions are very similar to SPI serial transactions - the protocol used over the two interfaces is identical.
http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial here's the low-level details you need http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_jtag_to_avalon_analysis.pdf http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_jtag_to_avalon_analysis.zip Create a testbench with the SPI-to-Avalon-MM component, and create SPI byte transactions with the protocol defined in this document. You'll see the IDLE codes being returned over SPI, and see how to form packets. The Tcl scripts in the above documents show how to create these packets from quartus_stp. Your SPI code would need to do the same. Cheers, Dave
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