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error while simulating in quartus

Altera_Forum
Honored Contributor II
1,558 Views

Hi,  

I'm trying to simulate a FSM, but I keep getting this error message:  

"Error: Zero-time oscillation in node "|top|FSMcontrol:L1|Selector5~0" at time 50.0 ns. Check the design or vector source file for combinational loop." 

 

Code:  

 

library ieee; 

use ieee.std_logic_1164.all; 

use IEEE.std_logic_unsigned.all; 

 

 

entity FSMcontrol is 

port( 

Clock_in: in std_logic; 

Reset_in: in std_logic; 

enable_reg: out std_logic; 

Clk: out std_logic; 

Rst: out std_logic; 

enable_inc: out std_logic; 

readd: out std_logic; 

writee: out std_logic 

); 

end FSMcontrol; 

 

 

architecture control of FSMcontrol is 

type STATES is (s_reset,s_increment,s_enable,s_user_write,s_user_read,delay1,delay2,delay3,delay4,d_clock_1,d_clock_2,d_clock_3); 

signal EA, PE: STATES; 

signal atraso: std_logic_vector(27 downto 0); 

 

 

 

 

begin 

 

 

Clk <= Clock_in; 

Rst <= Reset_in; 

 

 

process (Clock_in, Reset_in) 

begin 

 

 

if Reset_in = '0' then 

EA <= s_reset; 

 

elsif Clock_in'event and 

Clock_in = '1' then 

EA <= PE; 

end if; 

end process; 

 

 

process(EA) 

begin 

 

 

case EA is 

 

 

when s_reset => 

enable_reg <= '0'; enable_inc <= '0'; readd <= '0'; writee <= '0'; 

PE <= delay1; 

 

 

when s_increment => 

enable_reg <= '0'; enable_inc <= '1'; readd <= '0'; writee <= '0'; 

PE <= s_user_read; 

 

 

when s_user_read => 

enable_reg <= '0'; enable_inc <= '0'; readd <= '1'; writee <= '0'; 

PE <= s_enable; 

 

 

when s_enable => 

enable_reg <= '1'; enable_inc <= '0'; readd <= '0'; writee <= '0'; 

PE <= d_clock_1; 

 

 

when s_user_write => 

enable_reg <= '0'; enable_inc <= '0'; readd <= '0'; writee <= '1'; 

PE <= s_increment; 

 

 

when delay1 => atraso <= ( others => '0' ); 

PE <= delay2; 

 

when delay2 => atraso <= atraso + 1; 

PE <= delay3; 

 

 

when delay3 => if atraso >= x"8F0D180" then PE <= s_increment; 

else PE <= delay4; 

end if; 

 

 

when delay4 => PE <= delay2; 

when d_clock_1 => PE <= d_clock_2; 

when d_clock_2 => PE <= d_clock_3; 

when d_clock_3 => PE <= s_user_write; 

end case; 

end process; 

end control;
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Altera_Forum
Honored Contributor II
313 Views

atraso <= atraso + 1; 

 

you cannot put counters in an asynchronous process.
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Altera_Forum
Honored Contributor II
313 Views

 

--- Quote Start ---  

atraso <= atraso + 1; 

 

you cannot put counters in an asynchronous process. 

--- Quote End ---  

 

 

Oh, and how can I fix this?
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Altera_Forum
Honored Contributor II
313 Views

put the counter in a synchronous process.

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