using integer

[Altera_Forum]

Hi, 

 I have two questions about using integer in VHDL.  1. If I had to convert a std_logic_vector to an integer, is it better to use CONV_INTEGER(MyVector) or to_integer(unsigned(MyVector)) ?? Or is it the same?  2. If I had to communicate integer values between to blocks, should I use an Integer OUT / IN, or is it better to convert to std_logic_vector and reconvert to integer??  Thanks for your answers! Sim

[Altera_Forum]

1. use use ieee.numeric_std only. 

2. Depends... I use generics with integers and unsigned/slv between modules.

[Altera_Forum]

--- Quote Start ---  1. use use ieee.numeric_std only. 2. Depends... I use generics with integers and unsigned/slv between modules.  --- Quote End ---    - So you mean I should use to_integer(unsigned(MyVector)). Why? Any special reason? - If an integer value is calculated in one module, and used as an integer in an other modul, is it in this case useful to convert / reconvert or not?

[Altera_Forum]

std_logic_vector to integer conversion is undefined unless you are importing one of the non-IEEE arithmetic libraries STD_LOGIC_UNSIGNED respectively STD_LOGIC_SIGNED. 

 Regularly, std_logic_vector must be type casted to signed or unsigned before. Using IEEE.NUMERIC_STD, the conversion is   integer_signal <= to_integer(unsigned(slv_value)); or integer_signal <= to_integer(signed(slv_value));

[Altera_Forum]

Ok, that means to_integer(unsigned(slv_value)) is standardised and CONV_INTEGER(MyVector) isn't. 

 Right?

[Altera_Forum]

--- Quote Start ---  Ok, that means to_integer(unsigned(slv_value)) is standardised and CONV_INTEGER(MyVector) isn't.  Right?  --- Quote End ---    Yes. The latter comes from a package that was created by synopsis back in the late 80s early 90s, and became a bit of a defacto standard. Different vendors wrote their own versions of the libraries so back then they were all slightly different. Then the IEEE wrote numeric std which standadised it all in 1993. Unfortunately vendors did not get around to supporting it for a while so everyone got used to std_logic_unsinged/signed/arith and even more unfortunately a lot of examples and text books use the non standard packages (plus generated code and documentation from Xilinx STILL uses these libraries, ALtera generally uses numeric_std).    --- Quote Start ---   2. If I had to communicate integer values between to blocks, should I use an Integer OUT / IN, or is it better to convert to std_logic_vector and reconvert to integer??   --- Quote End ---    If its internal connection (ie not to device pins), then a constrained integer is fine. For top level, use std_logic_vector or unsigned/signed type. If it really is a number, you dont have to use std_logic_Vector anywhere unless you connect it to a megawizard block.

[Altera_Forum]

Using std_logic_vector all the time on ports leads to lots and lots of type conversion when you dont need to.,

[Altera_Forum]

Ok, thanks. So for internal connections I could use integer. 

Only for my understanding, why couldn't I connect an integer to the pins?

[Altera_Forum]

well an integer type in VHDL has no bits, so how can you map an integer that has no specific bits to individual pins? 

I think quartus isnt that stupid though so you can do it, I personally just wouldnt risk it - its safer to be able to directly map them.

[Altera_Forum]

--- Quote Start ---  well an integer type in VHDL has no bits, so how can you map an integer that has no specific bits to individual pins? I think quartus isnt that stupid though so you can do it, I personally just wouldnt risk it - its safer to be able to directly map them.  --- Quote End ---    Ok, I got it! Thanks.

[Altera_Forum]

Constrained integers (with a range specification) can be used instead of signed and unsigned port signals and Quartus generates the bit representation automatically. You'll notice that some Quartus VHDL templates are doing this. But this description style lacks a bit of clarity, I think.