remote update reconfig fails at low temperatures

[Altera_Forum]

We have a design that we've been using for a couple of years now, but have just noticed an issue at low temperatures. 

 The design uses a Stratix II EP2S30, an EPCS64 in fast AS mode, remote update, and Nios II. There are two images stored in the EPCS64: a "factory" config+app at offset 0, and an "update" config+app stored at another fixed offset. A modified EPCS bootloader detects whether the system is in factory or update mode, the reason for the last reconfig (powerup or logic-induced), and whether an update image exists on the flash. If in factory mode due to powerup, and an update exists, the device reconfigs from the update. If in update mode, the update app is executed. If in factory due to logic-induced reconfig (indicating a failed attempt to load an update image), the factory app is executed. Using this scheme, the same config and bootloader can be used in either location.  We have found that above 10 degrees C, everything works fine. The device loads the factory config, detects the presence of an update, and then reconfigs using the update and runs the update app. Reconfig takes about 188ms. At temperatures below 5C, however, the factory config loads, the device reconfigs from the update image, but the bootloader from the update image never executes. Instead, the FPGA immediately reconfigs with the factory image again. The remote update status register indicates the reconfig was due to the logic array (i.e. software or logic, not an external pin or watchdog [which we're not using]). Also, the attempt to reconfig with the update image only takes about 176ms instead of the normal 188ms.  I have tried several different versions of config files (from archives over the past couple of years), in both factory and update positions, and a couple of different boards, but the results are always consistent. Everything works normally above 10C, whatever is in factory always loads properly at any temp, but whatever is in update fails at lower temps with a shortened config time.  Any ideas?

[Altera_Forum]

The remote upgrade IP should work in a clock blew 40MHz.

[Altera_Forum]

The clock is provided by the FPGA. Other than selecting fast AS mode, I have no control over it. The compressed bitstream is just over 5e6 bits. At 188ms, that's a clock rate of 26.7MHz. This is consistent with the datasheet, which specifies a typical clock of 26MHZ for fast AS mode.