Qsys new component - file path keeps changing

[Altera_Forum]

Hello, 

 i am working on my first Qsys project and it is running smooth with all built in components and one custom unit i connected in my .bdf file.  However, i was trying to a add the I2C unit from Altera wiki by the following steps: 

1. New component (in Qsys) 
2. add the top module to files (i2c_opencores.v) 
3. Analyze file and connect all signal to the avalon counterpart and assign everything in interfaces and edit some names 
4. no errors or warnings appear and i save 
5. adding to system content is fine too 
6. THEN: when i edit the file again or just generate and compile in quartus i get the errors 

  edit again error: Error: add_fileset_file: No such file .../VHDL/i2c_opencores/vhdl/i2c_opencores/i2c_opencores.v the path is doubled??  same during compilation:  Error (12252): ...: add_fileset_file: No such file .../TDC_FPGA/VHDL/i2c_opencores/VHDL/i2c_opencores/i2c_opencores.v  no matter how often i specify the correct path it always returns to the wrong path!  Any ideas someone?  EDIT: i dont get this pathchange if i dont edit any names and leave everythin "as is".  EDIT2: however it also happens if i add multiple files!

[Altera_Forum]

I wonder why I2C is not included in QSys Library as a ready-to-use QSys component ...

[Altera_Forum]

I'm also having path problems with Qsys. 

 I have a QSYS SOPC system initially generated under Quartus 11.X (sp?).  There were problems with the hard PCIe core burst logic under Q11.X so when Quartus 12.0 came out I transferred to that and  everything appeared to work well.  Now I have another logic module to add to my QSYS system but it looks like Q12.0 qsys can't read Q11.X qsys files properly, it's totally ****ed up source file path names (I keep my source in a separate directory), it doesn't even select the top level file properly (even though this is specified in the *.qsys file).  I'm going to have to start from scratch with a fairly complex system. :-(  Have you changed Quartus versions at all?  Nial

[Altera_Forum]

Hi! 

I am facing same issues in QSYS 12.1 (SP1). File paths in Component Editor's "Synthesis Files" list change after selecting the specific source files (in my case 4 Verilog files). The wizard automatically adds additional folders in between.  e.g 3C25/fpga_src/subf/xx1.v changes to 3C25/3C25/fpga_src/subf/xx1.v  Adding another file adds another level to the first added file path: 3C25/3C25/3C25/fpga_src/subf/xx1.v Same a GZoinker, my source files are located in a separate directory rather than the main .qsys System file.  I have also seen this behavior on earlier versions (12.0, 12.1).   Any ideas why this happens? When finishing the Component Editor, QSYS wants to access the wrong paths, which does not work since they do not exist. Thanks!  EDIT: Workaround could be to manually edit paths in the xxx_hw.tcl file of the component. Then open again the Component Editor and continue to create the component.  It turned out that at least module name (tab1) should be identical to top level module name (tab2). Maybe either description below should be equal to module name either.

[Altera_Forum]

I have this observed this bug as well, using 12.1 sp1.. :( Hope for a bug-fix within long.

[Altera_Forum]

This unbelievably bad for a tool that we're supposed to be using to earn a living, you'd wonder how much 

testing has been done before release?  COME ON ALTERA, THIS ISN'T GOOD ENOUGH.  Nial

[Altera_Forum]

I'm having the same problem too. The Qsys 'details' dialog box shows the right path, but the component editor wouldn't allow me to change the faulty path regardless how many times i try. 

 I solved it by deleting the tcl, and remaking the component. Not a novel workaround perhaps? but there's nothing else i can do.

[Altera_Forum]

--- Quote Start ---  I'm having the same problem too. The Qsys 'details' dialog box shows the right path, but the component editor wouldn't allow me to change the faulty path regardless how many times i try.  I solved it by deleting the tcl, and remaking the component. Not a novel workaround perhaps? but there's nothing else i can do.  --- Quote End ---    Qsys Component editor gave me a lot of trouble.   The workaround that I am using right now is fairly simple until they fix the bug.   I use SOPC builder component editor. It is easier than the one in Qsys. My file system looks like this (A qsys subsystem that needs to integrate a custom component )   /Qsys_subsystem_alphaQsys_subsystem_alpha.qsys  Custom_component_hdl/ custom_component_top.vhd  custom_component_hw.tcl    When you open the subsystem with Qsys it will display the custom component and you can add it to your design. the _hw.tcl file is made by SOPC builder. It works for components with multiple synth files

[Altera_Forum]

I was hired as a consultant to help get a company out of this kind of mess (in 11.1). They were using component editor to create their own components. Finally, since all confidence was lost in this tool, and given the statement by one of their gurus that component editor was meant to just get the user started, I decided to isolate the design from the Qsys environment by adding a bridge to export the avalon bus signals. This way the user components simply hook up to the inteface outside of Qsys. You can put a separate bridge for each user component to keep things nice. The only issue is you have to add the base addresses to your C code since it won't be done by qsys. 

 Good luck.

[Altera_Forum]

--- Quote Start ---  I was hired as a consultant to help get a company out of this kind of mess (in 11.1). They were using component editor to create their own components. Finally, since all confidence was lost in this tool, and given the statement by one of their gurus that component editor was meant to just get the user started, I decided to isolate the design from the Qsys environment by adding a bridge to export the avalon bus signals. This way the user components simply hook up to the inteface outside of Qsys. You can put a separate bridge for each user component to keep things nice. The only issue is you have to add the base addresses to your C code since it won't be done by qsys.  Good luck.  --- Quote End ---    Interesting but it will be followed by a tidy work aligning data/address of your custom component with your bus. It might be feasible for Memory Mapped connection but it is certainly tricky for Avalon-ST connections. Giving that timing adapters are "freely" provided by Qsys.  Qsys is a good tool in general (one should not focus with only one aspect that failed), not yet mature and I am sure it will be better in newer versions of Altera design tools.  I managed to incorporate a custom JPEG encoder in a Qsys subsystem. I created the (_hw.tcl) file with SOPC builder. Then I added the folder that has the RTL and TCL files under the subsystem path. Qsys recognized the tcl file and displays the component in the top left among other components. I tested it and it worked.

[Altera_Forum]

--- Quote Start ---  Interesting but it will be followed by a tidy work aligning data/address of your custom component with your bus. It might be feasible for Memory Mapped connection but it is certainly tricky for Avalon-ST connections. Giving that timing adapters are "freely" provided by Qsys.  Qsys is a good tool in general (one should not focus with only one aspect that failed), not yet mature and I am sure it will be better in newer versions of Altera design tools.  I managed to incorporate a custom JPEG encoder in a Qsys subsystem. I created the (_hw.tcl) file with SOPC builder. Then I added the folder that has the RTL and TCL files under the subsystem path. Qsys recognized the tcl file and displays the component in the top left among other components. I tested it and it worked.  --- Quote End ---    I've worked on a couple of SOPC systems and although I thought it was really powerful, the setbacks due to GUI issues really leaves me feeling like looking for alternatives. The last system used their Ethernet MAC. Our stuff resides outside QSYS and inside is the MAC with the necessary ST modules and signals, which eventually get exported to our modules. You're doing well by working in only the TCL and HDL files. Its is a good idea as long as you have the knowledge and keep it fresh in your mind. I have to leave this design in another companies hands and staying away from the internal workings of Qsys has been working well.  Cheers

[Altera_Forum]

--- Quote Start ---  given the statement by one of their gurus that component editor was meant to just get the user started  --- Quote End ---    I agree with your customer's guru; if you're going to spend any amount of time creating/editing components, just do it via the TCL files. The GUI editor doesn't really bring much to the table and leaves much to be desired.

[Altera_Forum]

--- Quote Start ---  I agree with your customer's guru; if you're going to spend any amount of time creating/editing components, just do it via the TCL files. The GUI editor doesn't really bring much to the table and leaves much to be desired.  --- Quote End ---    Sorry for not being clear. It was an Altera guru that made the comment about the component editor. I share your sentiments about the GUI. Unfortunately we couldn't convince Altera that there is a bigger issue here.

[Altera_Forum]

--- Quote Start ---  Hello,  i am working on my first Qsys project and it is running smooth with all built in components and one custom unit i connected in my .bdf file.  However, i was trying to a add the I2C unit from Altera wiki by the following steps: 

1. New component (in Qsys)  
2. add the top module to files (i2c_opencores.v)  
3. Analyze file and connect all signal to the avalon counterpart and assign everything in interfaces and edit some names  
4. no errors or warnings appear and i save  
5. adding to system content is fine too  
6. THEN: when i edit the file again or just generate and compile in quartus i get the errors  

  edit again error: Error: add_fileset_file: No such file .../VHDL/i2c_opencores/vhdl/i2c_opencores/i2c_opencores.v the path is doubled??  same during compilation:  Error (12252): ...: add_fileset_file: No such file .../TDC_FPGA/VHDL/i2c_opencores/VHDL/i2c_opencores/i2c_opencores.v  no matter how often i specify the correct path it always returns to the wrong path!  Any ideas someone?  EDIT: i dont get this pathchange if i dont edit any names and leave everythin "as is".  EDIT2: however it also happens if i add multiple files!  --- Quote End ---    When using I2C Opencores via QSYS and then compiling in Quartus II v.13.0 I get "Warning (12251): I2c_opencores_0: i2c_opencores is not in the library" which results in Errors. In QSYS Generate went OK. What library is Quartus talking about?  Is it the same thing You were asking about? What is the way out?

[Altera_Forum]

A reply to myself: put all I2C Opencores Verilog files into the same directory where the Top project is located.

[Altera_Forum]

I'm just sending this quickly. Hopefully it helps. 

Often when you add a component in Qsys, you have to add a .qip file that is generated, not the top level hdl file. In the QIP file is a reference to all the hdl, sdc, tcl, etc. files. Sometimes you have to also make changes to sdc files (for example in the case of the ethernet MAC for clock frequencies) - this annoying problem is helped by copying the sdc into your own source directory and adding it to the project otherwise it will be overwritten everytime you run Qsys.  A third party design or custom design needs the _hw.tcl file (can be generated by the component editor but only do this once at the start, then edit it manually) and you have to put the file set in the Altera/release/ip directory. Qsys will scan it and make it available as a component and its source files will be included in the system QIP file.

[Altera_Forum]

I am also having this problem

[Altera_Forum]

I stopped using the component editor for these reasons. Its actually easier to work with hw.tcl files - learning curve is just a couple of hours. Also once you make one its easy to modify and make others.