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vhdl code for tic tac game

Altera_Forum
Honored Contributor II
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i am going to do project on simple game tic tac on vhdl. I am using 9 switch and and nine led for display and 2 led to indicate the winner. i am thinking to distinguish to play by flashing of LED. if first player press the switch than led will be on and when 2nd player press the switch than led will start to flash for infinite time. So any one please help me for this project. i am quite new for vhdl.

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Altera_Forum
Honored Contributor II
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So, what problems are you having implementing it?

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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

So, what problems are you having implementing it? 

--- Quote End ---  

 

 

i am using counter and is it possible to make odd count as a player 1 and even count as player 2.
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Altera_Forum
Honored Contributor II
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what? how about posting some code and the problems you're having/

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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

what? how about posting some code and the problems you're having/ 

--- Quote End ---  

 

 

LIBRARY ieee; 

USE ieee.std_logic_1164.all; 

USE ieee.std_logic_arith.all; 

 

entity tic_tac is 

port(S1,S2,S3,S4,S5,S6,S7,S8,S9: in std_logic; -- nine different switch  

clk : in std_logic; 

rst : in std_logic; 

G1,G2,G3,G4,G5,G6,G7,G8,G9: out std_logic; -- output diode 

D1,D2,D3 : out std_logic);-- standby lED and WINNER indicator led  

end tic_tac; 

 

architecture rtl of tic_tac is  

 

sig <= s1,s2,s3,s4,s5,s6,s7,s8,s9; 

count:integer:= 0; 

 

begin 

when rising_edge(sig);  

than count<= count+1; 

if count = '1'; 

elsif S1 = '1'; 

than G1 = '1'; 

elsif S2='1'; 

than G2 = '1'; 

elsif S3='1'; 

than G3 = '1'; 

elsif S4='1'; 

than G4 = '1'; 

elsif S5='1'; 

than G5 = '1'; 

elsif S6='1'; 

than G6 = '1'; 

elsif S7='1'; 

than G7 = '1'; 

elsif S8='1'; 

than G8 = '1'; 

elsif S9='1'; 

than G9 = '1'; 

end if; 

if count = '2'; 

elsif S1 = '1'; 

than G1 = '1'; 

elsif S2='1'; 

than G2 = '1'; 

elsif S3='1'; 

than G3 = '1'; 

elsif S4='1'; 

than G4 = '1'; 

elsif S5='1'; 

than G5 = '1'; 

elsif S6='1'; 

than G6 = '1'; 

elsif S7='1'; 

than G7 = '1'; 

elsif S8='1'; 

than G8 = '1'; 

elsif S9='1'; 

 

 

end rtl;
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Altera_Forum
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this is what i think but i done know it will work or not. i jus do it for count 2 only but i think i dont need count integer also only 1 and 0 count will be sufficent to declare palyer 1 and 2.

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Altera_Forum
Honored Contributor II
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Wow. A lot of syntax errors (is this really a copy and paste of your code.) 

I suggest you read a VHDL reference. Then re-write it and run it through a compiler to fix the syntax errors (on almost every line).
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Altera_Forum
Honored Contributor II
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LIBRARY ieee; 

USE ieee.std_logic_1164.all; 

USE ieee.std_logic_arith.all; 

 

entity tic_tac is 

port(S1: in std_logic; 

S2: in std_logic; 

S3: in std_logic; 

S4: in std_logic; 

S5: in std_logic; 

S6: in std_logic; 

S7: in std_logic; 

S8: in std_logic; 

S9: in std_logic; -- nine different switch -- 

clk : in std_logic; 

rst : in std_logic; 

G1: out std_logic; 

G2: out std_logic; 

G3: out std_logic; 

G4: out std_logic; 

G5: out std_logic; 

G6: out std_logic; 

G7: out std_logic; 

G8: out std_logic; 

G9: out std_logic; -- output diode 

D1,D2 : out std_logic);-- WINNER indicator led  

end tic_tac; 

 

architecture rtl of tic_tac is  

 

signal sig,count,l1p1,l2p1,l3p1,l4p1,l5p1,l6p1,l7p1,l8p1,l9p1,l1p2,l2p2,l3p2,l4p2,l5p2,l6p2,l7p2,l8p2,l9p2, 

player2 : std_logic;  

 

 

begin 

 

sig <= S1 or S2 or S3 or S4 or S5 or S6 or S7 or S8 or S9;  

g1<=l1p1 or (l1p2 and clk) ; 

g2<=l2p1 or (l2p2 and clk) ; 

g3<=l3p1 or (l3p2 and clk) ; 

g4<=l4p1 or (l4p2 and clk) ; 

g5<=l5p1 or (l5p2 and clk) ; 

g6<=l6p1 or (l6p2 and clk) ; 

g7<=l7p1 or (l7p2 and clk) ; 

g8<=l8p1 or (l8p2 and clk) ; 

g9<=l9p1 or (l9p2 and clk) ; 

 

 

 

process(sig,rst) 

begin 

 

if (rst='1') then  

count<= '0';  

elsif rising_edge(sig) then  

count <= not count; 

 

 

end if; 

end process; 

process(count,player2) 

begin 

 

------------------------------------------ 

---------two player were selected--------- 

------------------------------------------ 

if count ='0' then  

player2<='1'; 

else 

player2 <='0'; 

end if; 

end process;  

 

process(rst,S1,S2,s3,s4,s5,s6,s7,s8,s9) 

begin 

if rst = '1' then 

l1p1<= '0'; 

l2p1<= '0'; 

l3p1<= '0'; 

l4p1<= '0'; 

l5p1<= '0'; 

l6p1<= '0'; 

l7p1<= '0'; 

l8p1<= '0'; 

l9p1<= '0'; 

l1p2<= '0'; 

l2p2<= '0'; 

l3p2<= '0'; 

l4p2<= '0'; 

l5p2<= '0'; 

l6p2<= '0'; 

l7p2<= '0'; 

l8p2<= '0'; 

l9p2<= '0';  

 

elsif s1= '1' then  

l1p2<= count; 

l1p1<= not count; 

 

 

elsif s2 ='1' then 

l2p2<= count; 

l2p1<= not count; 

 

elsif s3 ='1' then 

l3p2<= count; 

l3p1<= not count; 

 

elsif s4 ='1' then 

l4p2<= count; 

l4p1<= not count; 

 

elsif s5 ='1' then 

l5p2<= count; 

l5p1<= not count; 

 

elsif s6 ='1' then 

l6p2<= count; 

l6p1<= not count; 

 

elsif s7 ='1' then 

l7p2<= count; 

l7p1<= not count; 

 

elsif s8 ='1' then 

l8p2<= count; 

l8p1<= not count; 

 

elsif s9 ='1' then 

l9p2<= count; 

l9p1<= not count; 

 

end if; 

 

 

 

end process; 

 

 

 

d1<=(l1p1 and l2p1 and l3p1) or (l1p1 and l5p1 and l9p1) or (l1p1 and l4p1 and l7p1) 

or(l4p1 and l5p1 and l6p1) or (l7p1 and l8p1 and l9p1) or (l7p1 and l5p1 and l3p1) or (l8p1 and l5p1 and l2p1) 

or (l9p1 and l6p1 and l3p1); 

 

d2<= (l1p2 and l2p2 and l3p2) or (l1p2 and l5p2 and l9p2) or (l1p2 and l4p2 and l7p2) 

or(l4p2 and l5p2 and l6p2) or (l7p2 and l8p2 and l9p2) or (l7p2 and l5p2 and l3p2) or (l8p2 and l5p2 and l2p2) 

or (l9p2 and l6p2 and l3p2);  

 

 

 

end rtl; 

 

 

 

this my code, and its working fine. i write code for testbench also it working but but i face lots of latches while load in FPGA board
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Altera_Forum
Honored Contributor II
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this my code, and its working fine. i write code for testbench also it working but but i face lots of latches while load in FPGA board

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Altera_Forum
Honored Contributor II
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Thats because you built a lot of latches. In an asynchronous process (most of your code) must assign all signals in ALL brancches (and remember that means you need an else on ALL if branches). 

 

I dont understand why you have a clock input, but nowhere in your code is it used as a clock. 

 

You are also missing signals from at least 1 sensitivity list.
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

Thats because you built a lot of latches. In an asynchronous process (most of your code) must assign all signals in ALL brancches (and remember that means you need an else on ALL if branches). 

 

I dont understand why you have a clock input, but nowhere in your code is it used as a clock. 

 

You are also missing signals from at least 1 sensitivity list. 

--- Quote End ---  

 

 

 

i need clock signal to toggle the output diodes. will u help me by indicating which part of the needed "else" coz i dont have time.. within 1 week i have to design these all stuff in PCB.
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Altera_Forum
Honored Contributor II
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In your code - every if statement must have an else, and ALL signals assigned ANYWHERE in the process MUST be assigned in EVERY if or elsif or else branch.

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Altera_Forum
Honored Contributor II
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And you cannot just assign it to itself to remember its state - that is a latch.

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Altera_Forum
Honored Contributor II
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Hey, i found this code very helpful. 

Thanks for that. 

it runs without any error but can u please tell me how to implement it on hardware. i have FPGA board available with me. But i dont know how to make interface between FPGA board and my LED board. 

 

please do rly
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