Quartus Master Clock Warning - PLL output driving 2nd PLL Input

[Altera_Forum]

PLL1: 2 different external 10MHz inputs; 100 MHz output (system clock); Normal Mode. 

PLL2: PLL1|Output (system clock) as input; 20 MHz output; Source-synchronous compensation Mode.  I need the 100MHz and 20MHz synchronized. My sdc file contains: create_clock -name {clk_A} -period 100.000 -waveform { 0.000 50.000 } [get_ports {clk_A}] create_clock -name {clk_B} -period 100.000 -waveform { 0.000 50.000 } [get_ports {clk_B}] derive_pll_clocks  I receive the following warnings: Warning (332087): The master clock for this clock assignment could not be derived. Clock: PLL2|altpll_component|auto_generated|pll1|clk[0] was not created. ->Warning (332036): Clock: PLL1|altpll_component|auto_generated|pll1|clk[0] found as a potential master clock candidate ->Warning (332036): Clock: PLL2|altpll_component|auto_generated|pll1|clk[0]~1 found as a potential master clock candidate  The cursory solution is to add -master_clock option, but I am taking advantage of 'derive_pll_clocks'. Is there a solution that takes advantage of 'derive_pll_clocks' ie, not manually defining 'create_generated_clock' for these two PLLs? I am relatively new to this and I am concerned that I may screw up manually defining the generated clocks, especially with the clock switching.  Thanks in advance.

[Altera_Forum]

I was able to get a response via mySupport on this issue. The short is that, for cascaded plls, one cannot use derive_pll_clocks in the .sdc file. 'create_generated_clock' is necessary. 

To help with this, they pointed to AN471 pg13-15 for creating the generated clock for a switchover PLL. They also suggest the following steps to help create the 'create_generated_clock' syntax. 1. Comment out derive_pll_clock in SDC 2. In tcl console window of TimeQuest, type derive_pll_clocks 3. tcl console window will update with the correct create_generated_clock constraints 4. copy the constraints and add into SDC file.  In short, this is what I ended with: create_generated_clock -source {PLL1|altpll_component|auto_generated|pll1|inclk[1]} -multiply_by 10 -duty_cycle 50.00 -name {PLL1|altpll_component|auto_generated|pll1|clk[0]~1} {PLL1|altpll_component|auto_generated|pll1|clk[0]}  create_generated_clock -add -source {PLL1|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 10 -duty_cycle 50.00 -name {PLL1|altpll_component|auto_generated|pll1|clk[0]} {PLL1|altpll_component|auto_generated|pll1|clk[0]}  create_generated_clock -source {PLL2|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 5 -duty_cycle 50.00 -name {PLL2|altpll_component|auto_generated|pll1|clk[0]} {PLL2|altpll_component|auto_generated|pll1|clk[0]} -master {PLL1|altpll_component|auto_generated|pll1|clk[0]}