Is it possible to write a design over PCIe into Flash?

[Altera_Forum]

Hi everyone, 

 I have the following problem: I'm working on a device with a JTAG interface which is only accessable while the device is outside its case. Once it is in its case the JTAG interface isn't accessible anymore.  This is why I thought about a design, which is able to connect the PCIe-HIP with the flash-memory of my FPGA. By this way it should be possible to write the Flash-File directly from the PC into the Flash-Memory via the PCIe-Interface. I know, the first Design has to be programmed using the JTAG-Interface, but this is no problem. I just want to have a tool to change the design afterwards.  Did already someone have the same problem? What do I need to write the File into the Flash-Memory? Are there already any design-examples or IP-Cores?  Currently I'm developing on the Arria II GX Development Kit.  Thanks for reading  Steffen

[Altera_Forum]

If you work out the bus cycle sequence required to write to flash (not that difficult), there is no reason why the cycles can't be generated from a remote system over the PCIe interface.

[Altera_Forum]

You mean I can connect the flash-device with the tri-state-circutry? 

And for the bus cycle sequence I can read the datasheet of the flash-device?  If this is so, than I also think this is easy.  And what about the flash-file? Do I have to write own Software to write it to the flash or do I simply have to put it in the flash?  Thank you  Steffen

[Altera_Forum]

Just connect the PCIe up as an avalon master that can access the flash the same way any other master (eg a nios cpu) would. 

And the same way you'd use the PCIe to access any other on-fpga resources.  I'd sort out a sane address map (the default ones are horrid!) so that you can read (and write if necessary) any fpga resources that can easily be assigned (or accessed through) avalon slaves. It'll probably make debugging and diagnosis a lot easier.

[Altera_Forum]

OK, I'll try it. 

 Thank you Steffen

[Altera_Forum]

I think I got this right: 

I added the EPCS Serial Flash Controller in QSYS to the PCIe HIP and exported the Conduit Endpoint. Then I routed the four conduits to the pins connected to the Flash-Memory. And in Assignments -> Device -> Device and Pin Options -> Dual-Purpose Pins I selected the four Pins (DCLK, Data[0], Data[1] and FLASH_nCE/nCSO) as "Use as regular I/O".  Any comments?  I think by this way I must be able to write the flash-file to the flash-memory (somehow), right?

[Altera_Forum]

If you have anything else on the fpga you might want to access, I'd use the PCIe to Avalon master interface and then connect the serial flash controller as one of the avalon slaves. That allows one PCIe BAR access multiple avalon slave components. 

That is easiest to setup if the base of the PCIe BAR is avalon address 0.

[Altera_Forum]

I don't know if the EPCS Serial Flash controller is still a good idea. The documentation is very poor and Altera says: "Altera does not publish the usage of the control and data registers." and "The core must be connected to a NIOS II processor.". 

I can't use a NIOS II because I can't buy the license! I just want to write from my Debian-Box over PCIe to the Flash-Memory. Isn't there a simple way to use a license free core and test it with the "pci_debug"-Tool?  http://www.ovro.caltech.edu/%7edwh/correlator/pdf/altera_pcie.zip  Is there a way to include the Altera EPCS-Driver into the Debug-Tool?

[Altera_Forum]

By the way: my flash is an EPCS64.

[Altera_Forum]

The slow nios are free - but are still quite a lot of LUTs. 

I'm not sure how small you can make one! But I'd expose the soft reset line and memory to the PCIe so you can copy down the code and then take the processor out of reset.  Hmmm... isn't the flash writing code released as C source? That probably means you can compile it for your host!

[Altera_Forum]

--- Quote Start ---  I don't know if the EPCS Serial Flash controller is still a good idea. The documentation is very poor and Altera says: "Altera does not publish the usage of the control and data registers." and "The core must be connected to a NIOS II processor.".  --- Quote End ---   Where did you get that from? The registers are described in http://www.altera.com/literature/ug/ug_embedded_ip.pdf on page 5-4 and there is nothing secret about them. In fact if you look the EPCS controller core is nothing more than a ROM containing a bootloader and a SPI master combined in a single address space. If you don't intend to use a Nios CPU you can just use a SPI master instead. IIRC the EPCS driver provided by Altera should even work in this case with little modification (basically configure it so that it doesn't use an offset from the controller's base address).