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Hi, I am trying - processing/start/start analysis and elaboration - in Quartus 2 for the following VHDL code:
code: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity ber_count is generic ( size : integer := 128); port ( clk : in std_logic; --clkp : in std_logic; enc_valid : in std_logic; dec_valid : in std_logic; enc_data : in std_logic_vector ((size-1) downto 0); dec_data : in std_logic_vector ((size-1) downto 0); error_count : out std_logic_vector (7 downto 0) ); end ber_count; architecture behavioral of ber_count is signal enc_buf, dec_buf : std_logic_vector ((size-1) downto 0); signal ecount : integer := 0; signal new_dec_data, new_enc_data : std_logic; signal global_frame_count : integer := 0; signal err : std_logic; begin load_encoded_data: process(enc_valid) begin if rising_edge(enc_valid) then enc_buf <= enc_data; new_enc_data <= '1'; global_frame_count <= global_frame_count + 1 ; -- if needed, we can use this value to calculate BER end if; end process; load_decoded_data : process(dec_valid) begin if rising_edge(dec_valid) then dec_buf <= dec_data; new_dec_data <= '1'; end if; end process; count_errors: process (clk) begin if rising_edge(clk) then if (new_enc_data = '1'and new_dec_data = '1') then new_enc_data <= '0'; new_dec_data <= '0'; for i in 0 to (size-1) loop err <= (enc_buf(i) xor dec_buf(i)) ; --if(enc_buf(i) = dec_buf(i)) then if (err = '1') then ecount <= ecount + 1 ; end if; end loop; end if; end if; end process; error_count <= std_logic_vector(to_unsigned(ecount, error_count'length)); -- typecast integer into std_logic_vector end behavioral; code description: As you might have guessed this is code for an error counter module which buffers output frame from encoder and decoder, and compares the two frames to find number of errors. I am relatively new at VHDL, so the code might be a bit dirty (actually very dirty -_-). errors: These are the errors I am getting : Error (10028): Can't resolve multiple constant drivers for net "new_dec_data" at ber_count.vhd(50) Error (10029): Constant driver at ber_count.vhd(41) Error (10028): Can't resolve multiple constant drivers for net "new_enc_data" at ber_count.vhd(50) Error (10029): Constant driver at ber_count.vhd(31) The indicated lines in the error message are denoted in Arial Black font in the code. How do I resolve this problem ? Thanks LeoLink Copied
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In simple words, a signal can't be asigned a value more than once in concurrent code or in more than one process.
In hardware terms, it's like two logic outputs driving one signal without a mux. You'll find more detailed information in your favourite VHDL text book.- Mark as New
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Thanks for your reply FvM.
Mistake looks so obvious now. I will need to move the signal manipulation to single process. Will do that and post again if encountered a problem. Thanks again.
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