- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
When I creating a MegaCore function you can choose VHDL, AHDL and Verilog but I want to know are these just wrappers around some HDL that implements the Megafunction? I've been told that all of Altera's Megafunctions are actually AHDL. Is that true?
thanks, joeLink Copied
3 Replies
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
All of Altera's low level stuff is AHDL (just have a look in any db folder) but more complicated IP is often just a wrapper around whatever the IP core was written in. Not all IP is developped in house at Altera, but Altera themselves tend to write new stuff now in Verilog/SV
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
--- Quote Start --- Is that true? --- Quote End --- No. Increasingly they're just written in System Verilog I believe. Nial
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Where did you learn that they are being written in SystemVerilog?
Respectfully, joe
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page