PHY Ethernet to optics without external chip

[Altera_Forum]

Hello! 

 Can anyone tell me, is it possible to create PHY ethernet on my Cyclone IV E using IP core or VHDL/Verilog?  I also found "Custom PHY" IP core. Can I use it for all devices in family(Cyclone) or only for devices with embedded transceivers?!  I know, that almost everyone use external PHY chip for using in copper 8P8C. But for transmitting to optics external PHY chip isn't required.

[Altera_Forum]

When having a look at the documentation (http://www.altera.com/literature/ug/ug_ethernet.pdf) on pages 4-26 and onwards, it looks like both FPGAs with transceivers and the ones with regular LVDS drivers and soft CRD are supported. Of course the best way to be sure the FPGA you choose will be able to handle it is to create a Quartus project with it and check that it compiles correctly. It will help also to find out if you are defining your I/Os correctly, especially when you try to compile single-ended and LVDS I/Os in the same banks. 

Check also that the TSE PMA output (1000-BASE X / SGMII) is compatible with the optical transceiver that you plan to use.

[Altera_Forum]

Thank's a lot for your reply. 

 Really, we are interesting in small Ethernet data rates, about 200 Mb/s. And we know that everyone use PHY in this case. What can you suggest? Can we do it without PHY?   Custom PHY megafunction is available only for transceiver FPGA's, but data rates starts from 620 Mb/s in that case. But if we want to work on lower speeds (about 200 Mb/s), is it necessary to place external PHY device on board or we can replace PHY chip by soft code or IP in FPGA (I mean create PHY using only resourses of FPGA).

[Altera_Forum]

For low Ethernet speeds (100Mbits/s) I don't think there are any options inside the FPGA. You will need an external PHY that you can connect to the TSE inside the FPGA though a standard MII or RMII interface. Those interfaces don't use transceivers, but a lot of pins (20 for MII if I remember correctly).

[Altera_Forum]

Is there some hardware restrictions in FPGA which don't allow to create PHY inside FPGA? Or I can create PHY inside the FPGA using HDL?

[Altera_Forum]

For a copper based Ethernet the PHY can't be created inside the FPGA because it has an analog driver part that you can't reproduce with the FPGA hardware. 

For an optical connection, you need first to check what kind of signal standard the optical driver is using, to see if it is compatible with the available I/O standards on the FPGA. If this works you shouldn't have any problem implementing the transmission part in HDL. I'm not so sure about the receiving part, especially the clock recovery process. I don't really know the optical Ethernet specification so I can't help you on that one.

[Altera_Forum]

Many thanks, we don't have any questions.