Hello Folks,
I have a multiprocessor system in an Altera FPGA running multiple NIOS2 processors. I want to introduce a power logic that will turn off a NIOS2 cpu if battery power becomes very low. As a preservation system, the architecture of the system some what like this....
[Power Control] --> Monitor Input current and battery voltage
| | |
| | ------> Nios2 (CPU1)
| ________> Nios2 (CPU2)
|__________> Nios2 (CPU3)
Have any one done something like this inside FPGA?. And is there any true power saving on this approach?. Or by the fact that the FPGA is lit whether is one core or three power consumption is the same.
Thank you.
