Hello,
I have one register in my design that I want to treat differently from others. Let's call this reg_A. All of my registers are asynchronous to any input clock, so I'm using set_max_delay. In this case, I want reg_A to have a smaller max delay from an input port than the rest of the registers in the design. So I wrote these constraints:
set_max_delay -from [get_ports {CPU_OE_FPGA1_L}] -to [get_registers *] 28.000
set_max_delay -from [get_ports {CPU_OE_FPGA1_L}] -to [get_register {reg_A}] 10.000
The problem is that timequest uses the maximum value of 28.000 ns for all registers. It supercedes the second constraint. How do I write the first constraint to exclude reg_A, so that it will have a max delay of 10.000 ns?
