Qsys generates. but analysis/synthesis error

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Qsys generates. but analysis/synthesis error

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Hi,

I'm facing this weird error and can't seem to get my design to compile.

http://www.altera.com/support/kdb/solutions/rd05272012_45.html

The work around suggested is weird. I tried increasing the ram size and adding a dummy address range extender component.

But it still doesn't work properly.

I've tried removing components from my design and deleting the db directory as well. But it still gives an error.

Has anybody faced/solved this?

Thanks

Zubair

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