Arria II GX VCCIO and Quartus I/O Standard Mismatch

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Arria II GX VCCIO and Quartus I/O Standard Mismatch

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In an existing design, I have discovered the following: I am using an Arria II GX FPGA and have the VCCIO for one of the banks tied to +3.3VDC on the baord. The VREF pin for this bank is also connected to +3.3VDC. Within Quartus, I have the "+2.5V" standard selected.

Questions:

1. Is this an acceptable scenario, or could this potentially cause damage to the FPGA?

2. Will the inputs on this bank be subject to the +2.5V input threholds as identified in the device handbook, or the +3.3V thresholds (or some other threshold values)?

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