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hi,
i have a vhdl code for matrix multiplication each element in a matrix is 16 bit. both matrices are in 8x8 order. firstly i created array-pack for define the matrix. in next step, me designed a program which representing the text document data of binary values in matrix format. then wrote a code which in structural way , in which two component representing the matrix form and 3rd component for matrix multiplication... me getting the each module output separately,.when am connecting all these programs by structural,am not getting the output.. what will be the reason?:(Link Copied
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Because you did it wrong?
Did you write a testbench? have you simulated it?- Mark as New
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am doing this program in altera model sim software. is there need of test bench here..i want to simulate it..
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you should always simulate all code you write for FPGA.
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