StratixI maximum input current

[Altera_Forum]

Hi, 

I'm looking for information about the absolute maximum input current a pin can handle before damage and the maximum current the PCI-clamp diodes can support. I'm using an EP1S60F1508 and I need to connect the FPGA with devices powered at 17V that accept a 3.3 LVTTL input, in standard conditions there is no problem but sometimes this devices broke and create a short between the power supply(17V) and the input resulting in a 17V put into the FPGA output pin, in order to protect the FPGA I'm thinking to use an isolation resistance and the internal PCI clamp diode, is that possible? Of course I know that the best solution is to use a buffer between the FPGA and the devices but I do not have space enough (this issue regards at least 700 pins). In the stratix handbook I've been able to find just this table (Table 4-1 pag 181)      Symbol Parameter  Conditions  Minimum  Maximum  Unit   IOUT DC output current, per pin  -25 40 mA     it means that the max input current is 40mA or 25mA? I need this information to choose the isolation resistance.  I hope my english is clear enough Thank you in advance

[Altera_Forum]

1. There's no maximum rating of PCI clamp diodes specified in the datasheet. Considering that the -25 mA output current is related to the high side transistor, I would also try to keep 25 mA for the clamp current. 

2. Don't forget that the PCI clamp diodes are disabled between power on and configuration end.

[Altera_Forum]

But how much is the maximum input current for an input pin of the FPGA ? 25mA or 40mA? 

And at pag 184 of stratix handbook there is this note:  (3)Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V for input currents less than 100 mA and periods shorter than 20 ns, or overshoot to the voltage shown in Table 4–9, based on input duty cycle for input currents less than 100 ma. The overshoot is dependent upon duty cycle of the signal. The DC case is equivalent to 100% duty cycle  It means that a current of 100mA is acceptable for short period?  I am assuming that the clamping voltage is 3.3 V+ 0.7 V = 4 V is this correct?  Thank you in advance

[Altera_Forum]

I told a reasoning why I opt for 25 mA (continuous) clamping current. There's a possibility that I underrate the FPGA ruggedness in this point, better than overrate. Dynamic output currents can be considerably higher than -25/+40 mA.  

 I understand that your overvoltage problem is related to continuous input current.  Another possible source of information is the Stratix Ibis file, it shows all kinds of pin V/I characteristics, including clamping operation.  I still wonder how you can be sure that the FPGA is correctly configured when the supply short happens.

[Altera_Forum]

If you apply 17v to 700 pins won't the overall thermal dissipation of the package be the limiting factor?

[Altera_Forum]

Hi, 

  --- Quote Start ---  If you apply 17v to 700 pins won't the overall thermal dissipation of the package be the limiting factor?  --- Quote End ---   this is an "impossible" case, the devices I'm talking about are pin driver with an input and an enable pin, so I have 350 of them but I don't expect all of them to broke at the same time.    --- Quote Start ---  I still wonder how you can be sure that the FPGA is correctly configured when the supply short happens.  --- Quote End ---   I expect the short to happen during regular operation when the FPGA is correctly programmed, the devices are powered after the FPGA anyway so I hope the clamping diodes are on. I'll look at the Ibis file, but you gave me a good answer, thank you for your help:)