help from transceiver expert

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

help from transceiver expert

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Hi,

I will be back to travel on new project using Altera startix V. It is my first work on this area and i need your help.

I try to implement the design example for Startix V GX on wikialtera for transceiver toolkit for four channel

and it work perfectly. But when I try to change the VHDL code of generator or for checker and lets the loopback, I get always indication “Yellow—Test is running but no data is locked” that mean that the data send by the generator is lost.

Any suggestion please.

Thanks

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