Select PLL in Arria V GT D3

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Select PLL in Arria V GT D3

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Hi Friends,

I read Arria V device handbook, CLK[0..3][p,n] are connected to FRACTIONALPLL_XO_Y27 and FRACTIONALPLL_XO_Y18.

So, how do I know which CLK is connected to FRACTIONALPLL_XO_Y18 will has compensation better ?

I compiled by Quartus and saw warning as below :

"Warning (177007): PLL(s) placed in location FRACTIONALPLL_X0_Y18_N0 do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks

Info (177008): PLL a5gt_sys_pll:pll_sys|a5gt_sys_pll_0002:a5gt_sys_pll_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL"

Input clock is CLK0p (pin AP32). How can I fix it.

Thanks

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