increase TSE throughput issue

[Altera_Forum]

Dear all,  

My board: DE2-115 Cyclone IV E I've managed to run Web server template which is available with board by using: -TSE 10/100/1000 Gbps -Nios cpu Economic -50MHz clock.  - and other required basic parts in sopc which I thing most of you are familiar with. The issue started here, when I tried to measure the max bandwidth for this board it doesn't accept more than 10 Mb as a throughput.  and the speed doesn't exceed than 6 Mbps.  I read an440 and follow some of the related suggestion to my project, but there's no optimization yet.  Does any one have an idea where the tweak could be?  could it be on the software part or hardware?   Thanks in advance to all of you

[Altera_Forum]

after code optimizations you have to play with TSE MAC fifo's depth, NIOS chaches dimensions, clock frequency, but don't expect do gain and order of magnitude in data troguhput.  

Which way did you measure the troughput? Using Web Server Template Application? Keep in mind that web-server gets website data from the Flash memory, I wonder if this couldn't significantly affect the overhead while fetching data.

[Altera_Forum]

Thanks memes for reply 

I used bwping  http://bwping.sourceforge.net/ it's free open source to measure bandwidth. easy to use. I've questoin about the things that you mentioned,  how to reach them? r they in sopc or a *.v files?  - TSE MAC fifo depth - NIOS chaches dimensions. (i think this one available only for /f cpu)

[Altera_Forum]

Always use SOPC Builder or Qsys to edit NIOSII systems. 

You are right, NIOSII/e doesn't have caches..

[Altera_Forum]

Thanks memes,  

I've tried to increase the fifo's depth, but it didn't make any optimization.  Thanks any way for your help.

[Altera_Forum]

Do you compile the software with optimisations? (-O2). It gives quite a speed bump from -O0 

Increasing the clock to 100MHz should help too (but be careful with timing requirements)

[Altera_Forum]

Thanks Daixiwen, you always the best, 

Where can I find (-O2)? is it in NIOSII? I've tried to find it but couldn't  I'll try to increase the clock thanks for the advice.  Regards,

[Altera_Forum]

If you are building from Eclipse it should be somewhere in the build options. 

If you are building from a makefile it should be somewhere in the CCFLAGS

[Altera_Forum]

Thanks a lot,  

I've tried it and it made changes, but still can't exceed more than 10 M bit.  Before it was 6 Mb as a max. now it's around 10 mb. Do you think I've to change some where in TSE in sopc?  Regards,

[Altera_Forum]

Well the other things to do would be to move to the Nios II/f version with caches, use a 100MHz system clock, and use some on-chip memory for packet data, as suggested in an 440 (http://www.altera.com/literature/an/an440.pdf).