Downloading ELF Process failed (DD2 uniphy on Stratix IV)

[Altera_Forum]

hello folks, 

 I am trying to create a external memory connection through DDR2 uniPHY controller on my Stratix IV DE4.   I was able to successfully compile and then program the board with SignalTap II , but when I try to run the software from eclipse am getting the classic ELF error message "Downloading ELF Process failed". I have checked my license and there is no problem. Some google results stands that it might me a pin assignment problem, all pins were assigned according to the board datasheet but I have some doubts about the following pins: - afi_clk_out , afi_half_clk_out: were assigned to board clock out pins  - the memory interface status signals: local_cal_fail, local_cal_success, local_init_done were assigned to GPIO pins   furthermore, the timing issues are dynamically generated and managed by the uniPHY tcl script.  In order to debug the design, I 've removed the uniPHY controller from the design and then the design worked correctly. Therefore am sure now that the problem is directly connected to the uniPHY.   While am trying to run the software, I also got in the console something like "pausing target processor not responding", does this have any connection to the problem? Could you give me some hints how to track the problem!

[Altera_Forum]

I have some good and bad news to shear with u.  

 The only way to find the exact problem was by loading the files directly to the onchip memory. first problem "or bug" was that all needed .hex and .mif files where not in the project root directory for some reason so I had to move them. After that I was able to proceed with the with installing the software to the board, then I was getting some memory conflict errors on eclipse. Therefore, I tried to check and update the (.mif)s from processing -> update memory initialization files.  I was getting the following critical warning:   -Critical Warning: Memory depth (10240) in the design file differs from memory depth (16384) in the Memory Initialization File "/project/onchip_memory.hex" -- setting initial value for remaining addresses to 0  I have found that this value is given for some reason (again!!) in onchip_memory.v, so I changed it to 16384 and remove the existing "db" and "incremental_db" directories and compile to create them again and this one was SOLVED.  The bad news is that I cannot get rid of the following warning - Critical Warning: Memory depth (40) in the design file differs from memory depth (64) in the Memory Initialization File "/project/DDR2uniPHY_p0_AC_ROM.hex" -- truncated remaining initial content value to fit RAM  for this one I don't have any idea what how I can fix this problem. Deleting the overflowing values does not resolve the problem.  any hints!