PCIE IP - Relation between PCIe core clk with the other signals?

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

PCIE IP - Relation between PCIe core clk with the other signals?

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Hi all,

I am using PCIe IP in my QSYS system generator in Single word completer , Completer only mode.

I am facing so many clock problems in the design and i want to sychronize our design with the PCIe core clk output.

The things we want to know are

1. What is the relation between the PCIe Core output clock and the bar0_read and write signals??

I am not able to find in the datasheet. If someone point to the source it ll be helpful.

2.In datasheet there are so many timing diagrams with one signal always named as "CLK" . What is this clk???

Thanks and Regards,

Iyan

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