Hi,
I am using Stratix iV Kit (S4GX230) that has external DDR3's connected to both top (1x16Bit dq) and bottom (4x16Bit dq) port.
Is is generally possible to share PLL/DLL of Altera UniPHY between top and bottom DDR3 Controller, assigning bottom controller as master, and top controller as slave?
Qsys generation and Analysis/Synthesis works well when configuring in PLL/DLL sharing mode, but Fitter comes up with the following error messages:
Error (176350): Can't fit fan-out of node ........_pll0:pll0|altpll:upll_memphy|altpll_grc3:auto_generated|clk[3] into a single clock region
Error (176367): Can't assign fan-out of node "......._pll0:pll0|altpll:upll_memphy|altpll_grc3:auto_generated|clk[3]" to the Dual-Regional Clock region from (0, 0) to (59, 96)
Just want to figure out if I am running into a general problem before spending hours of finding the reason why Fitter fails.
Thanks in advance.
