Help on AN638 XAUI Example using Stratix V GX

Altera_Forum · ‎05-29-2013

Hello everyone once again.

I have partially managed to run the AN638 (http://www.alterawiki.com/wiki/10-gbps_ethernet_mac_and_xaui_phy_interoperability_hardware_demonstration_reference_design) Reference design on a Stratix V GX (5SGXEA7K2F40C2).

First I've changed from Engineering Silicon to Production Silicon and recompiled the project (Quartus 12.1). After that, testing loopback until ALTPMA was successfull. But, when I try to test BCMPMA Loopback or SFP+ Loopback (by using one Avago AFBR-703SDZ SFP+ Interface and one loopback fiber optic cable) data simply doesn't return. Does anyone knows why this happens?

Thank you in advance.

Altera_Forum · ‎05-30-2013

Problem solved.

Some pins were wrong on Stratix V GX Project as the channel used.

Pins changed/wrong:

-NVMPROT was missing pin, probably a typo, since a VNMPROT was pinned from nowhere to nowhere. Pinned to PIN_F8 (HSMA_RX_D_P13);

-GPIO0_1 and GPIO1_1 are swapped (PIN_C10 and PIN_D10);

-SIVGX project used HSMA_(R/T)X_(P/N)[7..4] while SVGX was pinned to HSMA_(R/T)X_(P/N)[3..0]. Changed pins to SIVGX configuration. Refer to Stratix V GX Reference Manual for pinnage.

Hope that this helps anyone who tries to use this project.