define multicycle path on specific instant

[Altera_Forum]

Hi there, 

 I have a big design clocked @ 250MHz. One of the submodules in the design is a slow IP that works at max. freq. of 100MHz. All registers in the IP have a clock enable port (CE). I need to apply a multicycle path between all registers within the IP so that the path delay is 3*Tclk. How can I specify this in the SDC file to use with questa timing analyzer ?  The hierarchy to the instant is : /arith/fpu1  The multicycle paths should be applied on all registers within the fpu1  I'm using a Stratix IV device and Quartus II v 11.1  Thanks in advance

[Altera_Forum]

for a start, are you sure the data will be aligned correctly? you need to make sure the data is set up 2 clock cycles before the enable is high to ensure that the setup time wont be violated with these slack paths.  

 It might be easiest to just tell it to look for all registers in the path with wildcards:  set_multicycle_path -from [get_keepers {ent_name:inst_name|my_slow_entity:slow_entity_inst|*}] -to [get_registers {ent_name:inst_name|my_slow_entity:slow_entity_inst|*}] -setup 3 set_multicycle_path -from [get_keepers {ent_name:inst_name|my_slow_entity:slow_entity_inst|*}] -to [get_registers {ent_name:inst_name|my_slow_entity:slow_entity_inst|*}] -hold 2  This will then only get applied to valid paths - any connections that dont exist will be ignored (so if you have the registers A -> B -> C, it wont set up a path from A -> C because that connection doesnt exist).

[Altera_Forum]

Thanks for the fast reply 

   --- Quote Start ---   for a start, are you sure the data will be aligned correctly? you need to make sure the data is set up 2 clock cycles before the enable is high to ensure that the setup time wont be violated with these slack paths.   Yes, I guarantee the data alignment.  It might be easiest to just tell it to look for all registers in the path with wildcards:  set_multicycle_path -from [get_keepers {ent_name:inst_name|my_slow_entity:slow_entity_inst|*}] -to [get_registers {ent_name:inst_name|my_slow_entity:slow_entity_inst|*}] -setup 3 set_multicycle_path -from [get_keepers {ent_name:inst_name|my_slow_entity:slow_entity_inst|*}] -to [get_registers {ent_name:inst_name|my_slow_entity:slow_entity_inst|*}] -hold 2  This will then only get applied to valid paths - any connections that dont exist will be ignored (so if you have the registers A -> B -> C, it wont set up a path from A -> C because that connection doesnt exist).  Would U please rewrite the constraint with the specified hierarchy in my first post ? I just got confused just reading the syntax. I'm using VHDL, the instant name is fpu1 and the instantiated module is fpucorr =>    fpu1 : fpucorr port map ( ....);   Also I have other questions: Will the wildcards make the constraint propagate inside the fpu1 hierarchy ? Why did U choose 3 for setup and 2 for hold ?    --- Quote End ---     Thanks in advance

[Altera_Forum]

I have another question please : 

 I have multiple clock domains in my design. The data to be processed is written to registers that are working on clock1. The data processing elements are working on clock2. The two clocks are unrelated. I do not need to add any signal synchronizers as I'm sure that domain/clock2 will read the data registers @ domain/clock1 after a long time so that the register contents can be assumed static. I do not need the tool to perform timing analysis on the paths crossing the domains so, I should set false paths between the two domain. How can I set all paths between the two domains as false paths ? If I need in another case to set false paths between specific registers -the registers may be in different hierarchies- how can I do that ?

[Altera_Forum]

I would ALWAYS put a fifo across the domains for things like that,there is usually too much risk you'll catch it on a change at some point, so you'll get intermittant failures. But if you really have to do it, you can use the set_false_path command, with a similar setup to the multicycle path. 

 For your design, as far as I can tell:  set_multicycle_path -from [get_keepers {fpucorr:fpu1|*}] -to [get_registers {fpucorr:fpu1|*}] -setup 3  2 for hold because Ive always been of the understanding 1 less than the setup for hold was best.