Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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how to have the right comparison result with quartus

Altera_Forum
Honored Contributor II
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Hi 

I have write a vhdl module of comparison, with quartus, I have add it  

to the architecture with SopcBuilder, and call it from nios. 

In nios I don't have right result, I don't know why?? 

have any one any idea about???!! 

 

this is the part of my code: 

process (a) 

variable x,y : integer:=0; 

begin 

x := (conv_integer(a)); 

if x > 0 then y := 1; 

elsif x < 0 then y := 0;  

else y := 0; 

end if; 

b <= conv_std_logic_vector(y,32); 

end process; 

 

in the console of nios I have arbitrary zeros and ones.
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Altera_Forum
Honored Contributor II
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are you using std_logic_signed or std_logic_unsigned? (neither of these are part of the VHDL standard btw). 

 

In your code, Y will be 1 when A > 0, or 0 when A <= 0. If you are using std_logic_unsigned, Y will always be 1, unless A is 0.
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Altera_Forum
Honored Contributor II
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I have used the both of theme and I don't have good results

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